Bo Liu

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 15

Top Topics

Response Surface Methodology

Bp Neural Network Model

Particle Swarm Optimization

Top Venues

Microelectron. J.

Circuits Syst. Signal Process.

J. Circuits Syst. Comput.

Publications

Bo Liu, Pengfei Wang, Xiang Liu, Liwen Zhang
Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator. Microelectron. J. 143 (2024)
Jinchan Wang, Gefan Wang, Kai Li, Bo Liu
Erratum: A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology. J. Circuits Syst. Comput. 33 (9) (2024)
Jinchan Wang, Gefan Wang, Kai Li, Bo Liu
A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology. J. Circuits Syst. Comput. 33 (7) (2024)
Bo Liu, Weizhe Zhang, Wenjuan Duan, Qingduan Meng
BP Neural Network Modeling and Solving Acceleration of Analog ICs. Circuits Syst. Signal Process. 42 (12) (2023)
Haiyi Cai, Jincan Zhang, Min Liu, Shi Yang, Shaowei Wang, Bo Liu, Juwei Zhang
Adaptive particle swarm optimization based hybrid small-signal modeling of GaN HEMT. Microelectron. J. 137 (2023)
Bo Liu, Weizhe Zhang, Kai Li, Wenjuan Duan, Min Liu, Qingduan Meng
High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICs. Circuits Syst. Signal Process. 42 (4) (2023)
Bo Liu, Pengfei Wang, Kai Li, Binrui Xu, Jincan Zhang, Liwen Zhang
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout. Integr. 87 (2022)
Jun Wang, Yadan Zhang, Chunyan Hu, Pengjun Mao, Bo Liu
IACRA: Lifetime Optimization by Invulnerability-Aware Clustering Routing Algorithm Using Game-Theoretic Approach for Wsns. Sensors 22 (20) (2022)
Chao Geng, Bo Liu, Shigetoshi Nakatake
Density Optimization for Analog Layout Based on Transistor-Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. 23 (4) (2018)
Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake
Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. NGCAS (2017)
Chao Geng, Bo Liu, Shigetoshi Nakatake
Explicit layout pattern density controlling based on transistor-array-style. MWSCAS (2017)
Xuncheng Zou, Bo Liu, Shigetoshi Nakatake
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. ACM Great Lakes Symposium on VLSI (2017)
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig (2016)
Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
Twin-row-style for MOS analog layout. ICECS (2016)
Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. ISQED (2012)
Bo Liu, Bo Yang, Shigetoshi Nakatake
Layout-Aware Variability Characterization of CMOS Current Sources. IEICE Trans. Electron. (4) (2012)
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED (2011)
Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake
D-A converter based variation analysis for analog layout design. ASP-DAC (2010)