Qing Dong

Publication Activity (10 Years)

Years Active: 2008-2016
Publications (10 Years): 1

Top Topics

Low Power Consumption

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ACM Trans. Design Autom. Electr. Syst.

Publications

Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake
Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. ISVLSI (2015)
Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
Structured Analog Circuit and Layout Design with Transistor Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI (2013)
Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. VLSI-SoC (2013)
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED (2013)
Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED (2012)
Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. ACM Great Lakes Symposium on VLSI (2011)
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED (2011)
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
Structured analog circuit design and MOS transistor decomposition for high accuracy applications. ICCAD (2010)
Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. ISCAS (2010)
Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake
STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI (2009)
Qing Dong, Shigetoshi Nakatake
Structured Placement with Topological Regularity Evaluation. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI (2009)
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Qing Dong, Shigetoshi Nakatake
Constraint-free analog placement with topological symmetry structure. ASP-DAC (2008)