​
Login / Signup
Bo Yang
Publication Activity (10 Years)
Years Active: 2008-2018
Publications (10 Years): 3
Top Topics
Metal Oxide Semiconductor
Wavelet Packet Transform
High Speed
Layout Design
Top Venues
ISQED
ACM Trans. Design Autom. Electr. Syst.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
ICECS
</>
Publications
</>
Bo Liu
,
Gong Chen
,
Bo Yang
,
Shigetoshi Nakatake
Routable and Matched Layout Styles for Analog Module Generation.
ACM Trans. Design Autom. Electr. Syst.
23 (4) (2018)
Gong Chen
,
Toru Fujimura
,
Qing Dong
,
Shigetoshi Nakatake
,
Bo Yang
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.
ACM Trans. Design Autom. Electr. Syst.
21 (3) (2016)
Bo Liu
,
Shigetoshi Nakatake
,
Bo Yang
,
Gong Chen
Twin-row-style for MOS analog layout.
ICECS
(2016)
Bo Yang
,
Qing Dong
,
Jing Li
,
Shigetoshi Nakatake
Structured Analog Circuit and Layout Design with Transistor Array.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2013)
Gong Chen
,
Bo Yang
,
Yu Zhang
,
Qing Dong
,
Shigetoshi Nakatake
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.
ACM Great Lakes Symposium on VLSI
(2013)
Gong Chen
,
Yu Zhang
,
Bo Yang
,
Qing Dong
,
Shigetoshi Nakatake
A comparator energy model considering shallow trench isolation stress by geometric programming.
ISQED
(2013)
Yu Zhang
,
Gong Chen
,
Bo Yang
,
Jing Li
,
Qing Dong
,
Mingyu Li
,
Shigetoshi Nakatake
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2013)
Yu Zhang
,
Bo Liu
,
Bo Yang
,
Jing Li
,
Shigetoshi Nakatake
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
ISQED
(2012)
Qing Dong
,
Bo Yang
,
Gong Chen
,
Jing Li
,
Shigetoshi Nakatake
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
ISQED
(2012)
Bo Liu
,
Bo Yang
,
Shigetoshi Nakatake
Layout-Aware Variability Characterization of CMOS Current Sources.
IEICE Trans. Electron.
(4) (2012)
Gong Chen
,
Bo Yang
,
Shigetoshi Nakatake
,
Zhangcai Huang
,
Yasuaki Inoue
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
ISCAS
(2012)
Kota Shinohara
,
Mihoko Hidaka
,
Jing Li
,
Qing Dong
,
Bo Yang
,
Shigetoshi Nakatake
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.
ACM Great Lakes Symposium on VLSI
(2011)
Bo Liu
,
Qing Dong
,
Bo Yang
,
Jing Li
,
Shigetoshi Nakatake
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.
ISQED
(2011)
Bo Liu
,
Toru Fujimura
,
Bo Yang
,
Shigetoshi Nakatake
D-A converter based variation analysis for analog layout design.
ASP-DAC
(2010)
Bo Yang
,
Qing Dong
,
Jing Li
,
Shigetoshi Nakatake
Structured analog circuit design and MOS transistor decomposition for high accuracy applications.
ICCAD
(2010)
Jing Li
,
Bo Yang
,
Qing Dong
,
Shigetoshi Nakatake
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.
ISCAS
(2010)
Jing Li
,
Bo Yang
,
Xiaochuan Hu
,
Qing Dong
,
Shigetoshi Nakatake
STI stress aware placement optimization based on geometric programming.
ACM Great Lakes Symposium on VLSI
(2009)
Qing Dong
,
Bo Yang
,
Jing Li
,
Shigetoshi Nakatake
Incremental buffer insertion and module resizing algorithm using geometric programming.
ACM Great Lakes Symposium on VLSI
(2009)
Qing Dong
,
Bo Yang
,
Jing Li
,
Shigetoshi Nakatake
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2009)
Bo Yang
,
Shigetoshi Nakatake
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2009)
Bo Yang
,
Shigetoshi Nakatake
,
Hiroshi Murata
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver.
ISQED
(2008)
Bo Yang
,
Hiroshi Murata
,
Shigetoshi Nakatake
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(2) (2008)