Chip size estimation based on wiring area.

Yukiko Kubo Shigetoshi Nakatake Yoji Kajitani Masahiro Kawakita

Published in: APCCAS (2) (2002)

Keyphrases

search engine
high density
information retrieval
estimation accuracy
low cost
high speed
chip design
analog vlsi
accurate estimation
space complexity
standard deviation
building blocks
least squares
data sets
parameter estimation
circuit design
power dissipation
computational complexity