Shih-Hsu Huang

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 41

Top Venues

Publications

Liang-Ying Su, Shih-Hsu Huang
Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure. ISCAS (2024)
Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. ITC-Asia (2023)
Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li
Hardware Trojans of Computing-In-Memories: Issues and Methods. DFT (2023)
Hsin-Chen Lu, Shih-Hsu Huang
Fault-Tolerant Near-Memory MAC Design with Redundant Memories. ICCE-Taiwan (2023)
Chia-Jo Lin, Shih-Hsu Huang, Wan-Yi Hsueh, Wei-Chung Hsu, Chih-Wen Su
An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea. ICCE-Taiwan (2023)
Liang-Ying Su, Shih-Hsu Huang
A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging. ICCE-Taiwan (2023)
De-Yang Chiu, Shih-Hsu Huang
Dataflow and Hardware Design for The Sharing of Feature Maps. ISOCC (2022)
Hsu-Yu Kao, Shih-Hsu Huang
A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. AICAS (2022)
Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li
Design and Dataflow for Multibit SRAM-Based MAC Operations. ISOCC (2022)
Bo-Xi Lai, Shih-Hsu Huang, Hsu-Yu Kao
A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. ICCE-TW (2022)
De-Yang Chiu, Shih-Hsu Huang
Network Pruning by Feature Map Sharing with K-Means Clustering. ICCE-TW (2022)
En-Hui Zhang, Shih-Hsu Huang
Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing. ICCE (2021)
Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. ISOCC (2021)
Jia-Xiang Tang, Shih-Hsu Huang, Jui-Hung Hung
ECO Timing Optimization with Data Paths and Clock Paths Considered. ISPACS (2021)
Yi-Liang Hong, Yui-Kai Weng, Shih-Hsu Huang
Hardware Implementation for Fending off Side-Channel Attacks. ICCE-TW (2021)
Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao
Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. Sensors 21 (22) (2021)
Hsu-Yu Kao, Xin-Jia Chen, Shih-Hsu Huang
Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. Sensors 21 (15) (2021)
Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao
Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. ICCE-TW (2021)
Che-Wei Tung, Shih-Hsu Huang
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process. IEEE Access 8 (2020)
Xin-Jia Chen, Shih-Hsu Huang
Low-Power Small-Area $3\times 3$ Convolution Hardware Design. ICCE-TW (2020)
Shi-Rou Lin, Wei-Hung Lin, Shih-Hsu Huang, Chun-Lung Hsu, Chi-Tien Sun
Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. ICCE-TW (2020)
Yu-Hsuan Wu, Wei-Hung Lin, Shih-Hsu Huang
Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function. ICCE-TW (2020)
En-Hui Zhang, Shih-Hsu Huang
A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design. ICCE-TW (2020)
Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS (2020)
Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC (2019)
Po-Chieh Chang, Shih-Hsu Huang
IC Camouflaging by Using Universal Gates under Timing Constraints. ICCE-TW (2019)
Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang
A Design Framework for Hardware Approximation of Deep Neural Networks. ISPACS (2019)
Chih-Hsiang Chang, Hsu-Yu Kao, Shih-Hsu Huang
Hardware Implementation for Multiple Activation Functions. ICCE-TW (2019)
Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC (2019)
Chih-Hsiang Chang, En-Hui Zhang, Shih-Hsu Huang
Softsign Function Hardware Implementation Using Piecewise Linear Approximation. ISPACS (2019)
Shih-Hsu Huang
Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. NoCArc@MICRO (2018)
Yu-Yi Wu, Shih-Hsu Huang
TSV-aware 3D test wrapper chain optimization. VLSI-DAT (2018)
Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. ISOCC (2018)
Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ISOCC (2018)
Yen-Chun Ko, Shih-Hsu Huang
3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. ATS (2017)
Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake
Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD (2017)
Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Shih-Hsu Huang, Chun-Hua Cheng
Power-mode-aware buffer synthesis for low-power clock skew minimization. IEICE Electron. Express 13 (14) (2016)
Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake
Overview of the 2016 CAD contest at ICCAD. ICCAD (2016)
Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou
Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS (2016)
Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh
Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. 21 (1) (2015)
Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim
Overview of the 2015 CAD Contest at ICCAD. ICCAD (2015)
Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
Leakage-power-aware clock period minimization. DATE (2014)
Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang
Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew. APCCAS (2014)
Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang
Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. APCCAS (2014)
Shih-Hsu Huang, Hua-Hsin Yeh
Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2014)
Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang
Live demonstration: A low-power high-level synthesis system. APCCAS (2014)
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE (2013)
Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan
Low-power anti-aging zero skew clock gating. ACM Trans. Design Autom. Electr. Syst. 18 (2) (2013)
Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
Low-power timing closure methodology for ultra-low voltage designs. ICCAD (2013)
Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li
High-Level Synthesis for Minimum-Area Low-Power Clock Gating. J. Inf. Sci. Eng. 28 (5) (2012)
Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi
NBTI-aware dual threshold voltage assignment for leakage power reduction. ISCAS (2012)
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC (2012)
Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS (2012)
Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng
A formal approach to slack-driven high-level synthesis. ISCAS (2012)
Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng
Teaching three-dimensional system-in-package design automation in a semester course. MSE (2011)
Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng
Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27 (5) (2011)
Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang
Minimum Inserted Buffers for Clock Period Minimization. J. Inf. Sci. Eng. 27 (5) (2011)
Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang
TSV sharing through multiplexing for TSV count minimization in high-level synthesis. SoCC (2011)
Shih-Hsu Huang, Chun-Hua Cheng
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26 (6) (2010)
Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. ASP-DAC (2010)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14 (1) (2009)
Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang
Surge Current Minimization in High-level Synthesis. ISCAS (2009)
Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan
Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25 (6) (2009)
Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25 (6) (2009)
Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng
An ILP approach to surge current minimization in high-level synthesis. IEICE Electron. Express 6 (14) (2009)
Shih-Hsu Huang, Chun-Hua Cheng
Minimum-Period Register Binding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Shih-Hsu Huang, Chun-Hua Cheng
Timing driven power gating in high-level synthesis. ASP-DAC (2009)
Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu
Module binding for low power clock gating. IEICE Electron. Express 5 (18) (2008)
Shih-Hsu Huang, Chun-Hua Cheng
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu
Type-matching clock tree for zero skew clock gating. DAC (2008)
Shih-Hsu Huang, Chun-Hua Cheng
Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24 (6) (2008)
Shih-Hsu Huang, Yow-Tyng Nieh
Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops (2007)
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang
A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. EUC (2007)
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
Clock Period Minimization with Minimum Delay Insertion. DAC (2007)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23 (6) (2007)
Shih-Hsu Huang, Chun-Hua Cheng
Operation scheduling for the synthesis of false loop free circuits. IEICE Electron. Express 4 (14) (2007)
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS (2006)
Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai
High-Speed Fuzzy Inference Processor Using Active Rules Identification. JCIS (2006)
Shih-Hsu Huang, Chun-Hua Cheng
Operation Scheduling for False Loop Free Circuits. APCCAS (2006)
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
Peak Power Minimization through Power Management Scheduling. APCCAS (2006)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
State re-encoding for peak current minimization. ICCAD (2006)
Shih-Hsu Huang, Chun-Hua Cheng
An ILP Approach to the Slack Driven Scheduling Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2006)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC (2006)
Shih-Hsu Huang, Yow-Tyng Nieh
Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
Register binding for clock period minimization. DAC (2006)
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
Race-condition-aware clock skew scheduling. DAC (2005)
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
Minimizing peak current via opposite-phase clock tree. DAC (2005)
Shih-Hsu Huang, Jian-Yuan Lai
High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. J. Inf. Sci. Eng. 21 (3) (2005)
Shih-Hsu Huang, Chun-Hua Cheng
A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) (2005)
Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
Floorplanning with clock tree estimation. ISCAS (6) (2005)
Shih-Hsu Huang, Jian-Yuan Lai
A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. IEICE Trans. Inf. Syst. (10) (2005)
Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng
Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electron. Express 2 (4) (2005)
Shih-Hsu Huang, Yi-Rung Chen
VLSI implementation of type-2 fuzzy inference processor. ISCAS (4) (2005)
Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin
A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. IEICE Trans. Inf. Syst. (6) (2004)
Shih-Hsu Huang, Yow-Tyng Nieh
Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD (2003)
Shih-Hsu Huang, Yi-Siang Hsu
A timing driven approach for crosstalk minimization in gridded channel routing. APCCAS (1) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Shih-Hsu Huang