Wei-Kai Cheng

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 13

Top Topics

Linear Filtering

Power Reduction

Top Venues

J. Inf. Sci. Eng.

Publications

Hsin-Yi Pai, Wei-Kai Cheng
Framework and Quantization Method Design for CIM. ICCE-Taiwan (2023)
Yueh-Fan Lo, Wei-Kai Cheng
Convolutional Neural Network Accelerator for Integrated Winograd and Convolution Computations. ICCE-Taiwan (2023)
Hsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng
Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture. ISOCC (2022)
Wei-Kai Cheng, Xiang-Yi Liu, Tsai-Yu Tsai
Dataflow Design of Overlap-Add FFT on the Convolution Neural Networks. ICCE-TW (2020)
Wei-Kai Cheng, Yuan-Chih Lo, Hsia-Tsung Wang
Architecture Design of Overlap-Add FFT on the Convolution Neural Networks. ICCE-TW (2020)
Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS (2020)
Wei-Kai Cheng, Chih-Shuan Wu
Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement. ICCE-TW (2019)
Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. ISOCC (2018)
Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ISOCC (2018)
Wei-Kai Cheng, Yen-Heng Ciou, Po-Yuan Shen
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. Microprocess. Microsystems 42 (2016)
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
Unified approach for simultaneous functional and timing ECO. IET Circuits Devices Syst. 10 (6) (2016)
Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu
Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou
Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS (2016)
Wei-Kai Cheng, Po-Han Wu, Yi-Hsuan Chiu
A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes. J. Inf. Sci. Eng. 31 (5) (2015)
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
A logic difference generator with spare cells consideration for ECO synthesis. ISQED (2015)
Wei-Kai Cheng, Yen-Heng Ciou
A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM. ICS (2014)
Yi-Chun Yen, Jhih-Kai Yang, Wei-Kai Cheng
Memory binding and layer assignment for high-level synthesis of 3D ICs. APCCAS (2012)
Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi
A 3D IC designs partitioning algorithm with power consideration. ISQED (2012)
Wei-Kai Cheng, Youn-Long Lin
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4 (3) (1999)
Wei-Kai Cheng, Youn-Long Lin
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS (1998)
Wei-Kai Cheng, Youn-Long Lin
A Transformation-Based Approach for Storage Optimization. DAC (1995)
Wei-Kai Cheng, Youn-Long Lin
Code generation for a DSP processor. HLSS (1994)