Chun-Hua Cheng

Publication Activity (10 Years)

Years Active: 2005-2020
Publications (10 Years): 2

Top Topics

Wireless Transmission

Low Power Consumption

Top Venues

IEICE Electron. Express

Publications

Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS (2020)
Shih-Hsu Huang, Chun-Hua Cheng
Power-mode-aware buffer synthesis for low-power clock skew minimization. IEICE Electron. Express 13 (14) (2016)
Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang
Live demonstration: A low-power high-level synthesis system. APCCAS (2014)
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE (2013)
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC (2012)
Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS (2012)
Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng
A formal approach to slack-driven high-level synthesis. ISCAS (2012)
Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng
Teaching three-dimensional system-in-package design automation in a semester course. MSE (2011)
Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng
Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27 (5) (2011)
Shih-Hsu Huang, Chun-Hua Cheng
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26 (6) (2010)
Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang
Surge Current Minimization in High-level Synthesis. ISCAS (2009)
Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan
Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25 (6) (2009)
Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25 (6) (2009)
Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng
An ILP approach to surge current minimization in high-level synthesis. IEICE Electron. Express 6 (14) (2009)
Shih-Hsu Huang, Chun-Hua Cheng
Minimum-Period Register Binding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Shih-Hsu Huang, Chun-Hua Cheng
Timing driven power gating in high-level synthesis. ASP-DAC (2009)
Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu
Module binding for low power clock gating. IEICE Electron. Express 5 (18) (2008)
Shih-Hsu Huang, Chun-Hua Cheng
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Shih-Hsu Huang, Chun-Hua Cheng
Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24 (6) (2008)
Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops (2007)
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
Clock Period Minimization with Minimum Delay Insertion. DAC (2007)
Shih-Hsu Huang, Chun-Hua Cheng
Operation scheduling for the synthesis of false loop free circuits. IEICE Electron. Express 4 (14) (2007)
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS (2006)
Shih-Hsu Huang, Chun-Hua Cheng
Operation Scheduling for False Loop Free Circuits. APCCAS (2006)
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
Peak Power Minimization through Power Management Scheduling. APCCAS (2006)
Shih-Hsu Huang, Chun-Hua Cheng
An ILP Approach to the Slack Driven Scheduling Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2006)
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
Register binding for clock period minimization. DAC (2006)
Shih-Hsu Huang, Chun-Hua Cheng
A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) (2005)
Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng
Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electron. Express 2 (4) (2005)