Power-mode-aware buffer synthesis for low-power clock skew minimization.

Shih-Hsu Huang Chun-Hua Cheng

Published in: IEICE Electron. Express (2016)

Keyphrases

power consumption
low power
power management
high power
power saving
high speed
single chip
clock frequency
power dissipation
power reduction
digital signal processing
low power consumption
wireless transmission
energy saving
vlsi architecture
low cost
logic circuits
vlsi circuits
cmos technology
gate array
duty cycle