Yow-Tyng Nieh

Publication Activity (10 Years)

Years Active: 2003-2016
Publications (10 Years): 1

Top Topics

Low Power Consumption

Top Venues

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh
Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. 21 (1) (2015)
Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
Leakage-power-aware clock period minimization. DATE (2014)
Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
Low-power timing closure methodology for ultra-low voltage designs. ICCAD (2013)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14 (1) (2009)
Shih-Hsu Huang, Yow-Tyng Nieh
Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
Clock Period Minimization with Minimum Delay Insertion. DAC (2007)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23 (6) (2007)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
State re-encoding for peak current minimization. ICCAD (2006)
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC (2006)
Shih-Hsu Huang, Yow-Tyng Nieh
Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
Register binding for clock period minimization. DAC (2006)
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
Race-condition-aware clock skew scheduling. DAC (2005)
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
Minimizing peak current via opposite-phase clock tree. DAC (2005)
Shih-Hsu Huang, Yow-Tyng Nieh
Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD (2003)