Low-power timing closure methodology for ultra-low voltage designs.
Wen-Pin TuChung-Han ChouShih-Hsu HuangShih-Chieh ChangYow-Tyng NiehChien-Yung ChouPublished in: ICCAD (2013)
Keyphrases
- low power
- low voltage
- cmos technology
- high speed
- power consumption
- mixed signal
- low cost
- power management
- nm technology
- power line
- single chip
- vlsi circuits
- design considerations
- digital signal processing
- logic circuits
- low power consumption
- power dissipation
- frame rate
- vlsi architecture
- power reduction
- cost effective
- gate array
- design methodology
- parallel processing