Tsai-Ming Hsieh

Publication Activity (10 Years)

Years Active: 2000-2016
Publications (10 Years): 1

Top Topics

Unsupervised Segmentation

Functional Analysis

Color And Texture Features

Top Venues

IET Circuits Devices Syst.

Publications

Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
Unified approach for simultaneous functional and timing ECO. IET Circuits Devices Syst. 10 (6) (2016)
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
A logic difference generator with spare cells consideration for ECO synthesis. ISQED (2015)
Chin-Hung Su, Mohd Helmy Abd Wahab, Tsai-Ming Hsieh
Image Retrieval based on color and texture features. FSKD (2012)
Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh
A new ECO technology for functional changes and removing timing violations. ISQED (2011)
Hsin-Hsiung Huang, Jui-Hung Hung, Cheng-Chiang Lin, Tsai-Ming Hsieh
Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2011)
Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh
Technology remapping for engineering change with wirelength consideration. ISCAS (2010)
Hsi-An Chien, Cheng-Chiang Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh
Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2010)
Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh
Timing-driven X-architecture router among rectangular obstacles. ISCAS (2008)
Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. ISCAS (2008)
Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh
A congestion-driven buffer planner with space reservation. ISCAS (2006)
Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang
A new congestion and crosstalk aware router. ISCAS (6) (2005)
Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
Floorplanning with clock tree estimation. ISCAS (6) (2005)
Yi-Lin Hsieh, Tsai-Ming Hsieh
A New Effective Congestion Model in Floorplan Design. DATE (2004)
Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh
Structural Decomposition with Functional Considerations for Low Power. ISQED (2002)
Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh
An efficient hierarchical approach for general floorplan area minimization. APCCAS (2) (2002)
Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh
Sequence-pair based placement with boundary constraints. ISCAS (1) (2002)
Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh
A New Formulation for SOC Floorplan Area Minimization Problem. DATE (2002)
Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ISCAS (5) (2001)
Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). FPGA (2000)
Kuo-Chih Hsu, Yu-Chung Lin, Po-Xun Chiu, Tsai-Ming Hsieh
Minimum crosstalk channel routing with dogleg. ISCAS (2000)