Youn-Long Lin

ORCID

Publication Activity (10 Years)

Years Active: 1987-2023
Publications (10 Years): 12

Top Venues

CoRR

BMVC

DFUC@MICCAI

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao
NeighborTrack: Single Object Tracking by Bipartite Matching with Neighbor Tracklets and Its Applications to Sports. CVPR Workshops (2023)
Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang
SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. CoRR (2022)
Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin
HarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation. DFUC@MICCAI (2022)
Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao
NeighborTrack: Improving Single Object Tracking by Bipartite Matching with Neighbor Tracklets. CoRR (2022)
Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin
HarDNet-DFUS: An Enhanced Harmonically-Connected Network for Diabetic Foot Ulcer Image Segmentation and Colonoscopy Polyp Segmentation. CoRR (2022)
Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang
SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. BMVC (2022)
Hung-Yu Wu, Youn-Long Lin
HarDNet-BTS: A Harmonic Shortcut Network for Brain Tumor Segmentation. BrainLes@MICCAI (1) (2021)
Chien-Hsiang Huang, Hung-Yu Wu, Youn-Long Lin
HarDNet-MSEG: A Simple Encoder-Decoder Polyp Segmentation Neural Network that Achieves over 0.9 Mean Dice and 86 FPS. CoRR (2021)
Chien-Yao Wang, Hong-Yuan Mark Liao, I-Hau Yeh, Yung-Yu Chuang, Youn-Long Lin
Exploring the power of lightweight YOLOv4. ICCVW (2021)
Chao-Yang Kao, Huang-Chih Kuo, Jian-Wen Chen, Chiung-Liang Lin, Pin-Han Chen, Youn-Long Lin
RNNAccel: A Fusion Recurrent Neural Network Accelerator for Edge Intelligence. CoRR (2020)
Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin
HarDNet: A Low Memory Traffic Network. ICCV (2019)
Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin
HarDNet: A Low Memory Traffic Network. CoRR (2019)
Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access 1 (2013)
Huang-Chih Kuo, Youn-Long Lin
VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao
Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Huang-Chih Kuo, Youn-Long Lin
A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames. IEEE Trans. Multim. 14 (3-1) (2012)
Huang-Chih Kuo, Youn-Long Lin
A simple and effective lossless compression algorithm for video display frames. ICME (2011)
Chia-Ming Hung, Youn-Long Lin
Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. IET Comput. Digit. Tech. 5 (3) (2011)
Huan-Kai Peng, Youn-Long Lin
An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. ACM Trans. Embed. Comput. Syst. 9 (4) (2010)
Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC (2010)
Chao-Yang Kao, Cheng-Long Wu, Youn-Long Lin
A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Jian-Wen Chen, Li-Cian Wu, Po-Sheng Liu, Youn-Long Lin
A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video. IEEE Trans. Consumer Electron. 56 (4) (2010)
Ping Chao, Youn-Long Lin
An elastic software cache with fast prefetching for motion compensation in video decoding. CODES+ISSS (2010)
Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC (2010)
Chao-Yang Kao, Youn-Long Lin
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Li-Cian Wu, Youn-Long Lin
A High throughput CABAC Encoder for Ultra High Resolution Video. ISCAS (2009)
Jian-Wen Chen, Youn-Long Lin
A high-performance hardwired CABAC decoder for ultra-high resolution video. IEEE Trans. Consumer Electron. 55 (3) (2009)
Yuan-Chun Lin, Youn-Long Lin
A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. IEEE Trans. Very Large Scale Integr. Syst. 17 (6) (2009)
Huang-Chih Kuo, Jian-Wen Chen, Youn-Long Lin
A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. ESTIMedia (2009)
Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo, Youn-Long Lin
An effective dictionary-based display frame compressor. ESTIMedia (2009)
Chao-Yang Kao, Youn-Long Lin
A high-performance and memory-efficient architecture for H.264/AVC motion estimation. ICME (2008)
Ping Chao, Youn-Long Lin
Reference frame access optimization for ultra high resolution H.264/AVC decoding. ICME (2008)
Huang-Chih Kuo, Youn-Long Lin
An H.264/AVC full-mode intra-frame encoder for 1080HD video. ICME (2008)
Ping Chao, Youn-Long Lin
A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ISCAS (2008)
Cheng-Long Wu, Chao-Yang Kao, Youn-Long Lin
A high performance three-engine architecture for H.264/AVC fractional motion estimation. ICME (2008)
Jian-Wen Chen, Youn-Long Lin
A High-Performance Hardwired CABAC Decoder. ICASSP (2) (2007)
Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
Integration, Verification and Layout of a Complex Multimedia SOC CoRR (2007)
Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin
Introduction to H.264 advanced video coding. ASP-DAC (2006)
Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. APCCAS (2006)
Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
A near optimal deblocking filter for H.264 advanced video coding. ASP-DAC (2006)
Chao-Yang Kao, Huang-Chih Kuo, Youn-Long Lin
High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. ICME (2006)
Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
Integration, Verification and Layout of a Complex Multimedia SOC. DATE (2005)
Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ISCAS (5) (2005)
Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
An AMBA-compliant deblocking filter IP for H.264/AVC. ISCAS (5) (2005)
Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin
A platform based SOC design methodology and its application in image compression. Int. J. Embed. Syst. 1 (1/2) (2005)
Tien-Wei Hsieh, Youn-Long Lin
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. ESTIMedia (2004)
Yih-Chih Chou, Youn-Long Lin
Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (1) (2002)
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium (2002)
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium (2002)
Yih-Chih Chou, Youn-Long Lin
A 3-step approach for performance-driven whole-chip routing. ASP-DAC (2001)
Yih-Chih Chou, Youn-Long Lin
A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD (2001)
Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. ISSS (2001)
Hong-Kai Chang, Youn-Long Lin
Array allocation taking into account SDRAM characteristics. ASP-DAC (2000)
Tzu-Chieh Tien, Youn-Long Lin
Performance-optimal clustering with retiming for sequential circuits. ASP-DAC (2000)
Michael C.-J. Lin, Youn-Long Lin
A VLSI implementation of the blowfish encryption/decryption algorithm. ASP-DAC (2000)
Wei-Kai Cheng, Youn-Long Lin
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4 (3) (1999)
Yun-Yin Lian, Youn-Long Lin
Layout-based Logic Decomposition for Timing Optimization. ASP-DAC (1999)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC (1999)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Yih-Chih Chou, Youn-Long Lin
A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD (1998)
Wei-Kai Cheng, Youn-Long Lin
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS (1998)
Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
Integrating logic retiming and register placement. ICCAD (1998)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD (1998)
Youn-Long Lin
Recent developments in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 2 (1) (1997)
Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
Preserving HDL synthesis hierarchy for cell placement. ISPD (1997)
Youn-Long Lin
Computing brokerage and its application in VLSI design. ASP-DAC (1997)
Hsiao-Pin Su, Youn-Long Lin
A phase assignment method for virtual-wire-based hardware emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Youn-Long Lin, Tsung-Yi Wu
Storage optimization by replacing some flip-flops with latches. EURO-DAC (1996)
Tsung-Yi Wu, Youn-Long Lin
Register minimization beyond sharing among variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
Tsung-Yi Wu, Youn-Long Lin
Register Minimization beyond Sharing among Variables. DAC (1995)
Yu-Wen Tsay, Youn-Long Lin
A row-based cell placement method that utilizes circuit structural properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
Wei-Kai Cheng, Youn-Long Lin
A Transformation-Based Approach for Storage Optimization. DAC (1995)
Allen C.-H. Wu, Youn-Long Lin
High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. (3) (1995)
Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC (1994)
Wei-Kai Cheng, Youn-Long Lin
Code generation for a DSP processor. HLSS (1994)
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (2) (1994)
Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
State Assignment for Power and Area Minimization. ICCD (1994)
Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (3) (1993)
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD (1993)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
An effective methodology for functional pipelining. ICCAD (1992)
Yirng-An Chen, Youn-Long Lin, Long-Wen Chang
A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers 41 (1) (1992)
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40 (6) (1991)
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC (1991)
Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
Channel density reduction by routing over the cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
Channel Density Reduction by Routing Over The Cells. DAC (1991)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
Scheduling for Functional Pipelining and Loop Winding. DAC (1991)
Ta-Yung Liu, Youn-Long Lin
FLORA: A data path allocator based on branch-and-bound search. Integr. 11 (1) (1991)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (2) (1990)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC (1990)
Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
Data Path Allocation Based on Bipartite Weighted Matching. DAC (1990)
Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (7) (1990)
Youn-Long Lin, Yu-Chin Hsu
A new algorithm for tile generation. Integr. 9 (3) (1990)
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
LiB: A Cell Layout Generator. DAC (1990)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (10) (1989)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
Routing using a pyramid data structure. ICCAD (1989)

Youn-Long Lin.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Youn-Long Lin