Kuo-Liang Cheng

Publication Activity (10 Years)

Years Active: 2000-2007
Publications (10 Years): 0

Publications

Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Design and test of a scalable security processor. ASP-DAC (2005)
Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
An SOC Test Integration Platform and Its Industrial Realization. ITC (2004)
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
Fault Pattern Oriented Defect Diagnosis for Memories. ITC (2003)
Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD (2003)
Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Test and Diagnosis of Word-Oriented Multiport Memories. VTS (2003)
Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (11) (2002)
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium (2002)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA (2002)
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium (2002)
Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS (2002)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC (2001)
Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. VTS (2001)
Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC (2001)
Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium (2001)
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD (2000)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS (2000)