Chi-Feng Wu

Publication Activity (10 Years)

Years Active: 1999-2017
Publications (10 Years): 1

Top Topics

Design Space Exploration

Conceptual Model

High Level Synthesis

Top Venues

Publications

Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT (2017)
Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu
Apply high-level synthesis design and verification methodology on floating-point unit implementation. VLSI-DAT (2014)
Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang
. DATE (2014)
Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT (2013)
Shiueng-Bien Yang, Chi-Feng Wu
Locating Text in Images Based on the Smooth Gray-Level Detection. Int. J. Image Graph. 12 (4) (2012)
Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu
Test for more than pass/fail using on-chip temperature sensor. VLSI-DAT (2012)
Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee
Applying a Functional Neurofuzzy Network to Real-Time Lane Detection and Front-Vehicle Distance Measurement. IEEE Trans. Syst. Man Cybern. Part C 42 (4) (2012)
Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee
A functional neural fuzzy network for classification applications. Expert Syst. Appl. 38 (5) (2011)
Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC (2009)
Chenn-Jung Huang, You-Jia Chen, Chi-Feng Wu, Yi-An Huang
Application of neural networks and genetic algorithms to the screening for high quality chips. Appl. Soft Comput. 9 (2) (2009)
Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS (2007)
Hsiao-Hwa Chen, Chi-Feng Wu
A novel approach to enable decorrelating multiuser detection without matrix inversion operations. Int. J. Commun. Syst. 17 (9) (2004)
Hsiao-Hwa Chen, Jin-Xiao Lin, Shin-Wei Chu, Chi-Feng Wu, Guo-Sheng Chen
Isotropic air-interface technologies for fourth generation wireless communications. Wirel. Commun. Mob. Comput. 3 (6) (2003)
Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. 52 (4) (2003)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
Image Processing Techniques for Wafer Defect Cluster Identification. IEEE Des. Test Comput. 19 (2) (2002)
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. 18 (6) (2002)
Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA (2002)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC (2001)
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium (2001)
Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao
Single-ended SRAM with high test coverage and short test time. IEEE J. Solid State Circuits 35 (1) (2000)
Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
Collaboration between Industry and Academia in Test Research. Asian Test Symposium (2000)
Chi-Feng Wu, Cheng-Wen Wu
Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI Design 2000 (3) (2000)
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD (2000)
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS (2000)
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium (2000)
Chi-Feng Wu, Cheng-Wen Wu
Testing Interconnects of Dynamic Reconfigurable FPGAs. ASP-DAC (1999)
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES: A Fast Memory Fault Simulator. DFT (1999)
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16 (1) (1999)