Chao-Wen Tzeng

Publication Activity (10 Years)

Years Active: 2007-2015
Publications (10 Years): 0

Top Topics

Video Super Resolution

Process Management

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT (2015)
Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT (2013)
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng
Cell-Based Process Resilient Multiphase Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. VLSI-DAT (2012)
Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao
A fully cell-based design for timing measurement of memory. ITC (2011)
Chao-Wen Tzeng, Shi-Yu Huang
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT (2010)
Chao-Wen Tzeng, Shi-Yu Huang
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Chao-Wen Tzeng, Shi-Yu Huang
QC-Fill: An X-Fill method for quick-and-cool scan test. DATE (2009)
Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Chao-Wen Tzeng, Shi-Yu Huang
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Des. Test Comput. 25 (2) (2008)
Chao-Wen Tzeng, Shi-Yu Huang
Two-Gear Low-Power Scan Test. ATS (2008)
Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13 (1) (2008)
Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang
Robust paradigm for diagnosing hold-time faults in scan chains. IET Comput. Digit. Tech. 1 (6) (2007)
Chao-Wen Tzeng, Shi-Yu Huang
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain. IEEE Trans. Circuits Syst. II Express Briefs (8) (2007)