Hsuan-Jung Hsu

Publication Activity (10 Years)

Years Active: 2007-2013
Publications (10 Years): 0

Top Topics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC (2011)
Hsuan-Jung Hsu, Shi-Yu Huang
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT (2010)
Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu
-Tuning Scheme With Speed-Margining for Low-Power SRAM. IEEE J. Solid State Circuits 44 (10) (2009)
Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang
Built-In Speed Grading with a Process-Tolerant ADPLL. ATS (2007)