-Tuning Scheme With Speed-Margining for Low-Power SRAM.

Ya-Chun Lai Shi-Yu Huang Hsuan-Jung Hsu

Published in: IEEE J. Solid State Circuits (2009)

Keyphrases

low power
high speed
power consumption
low cost
single chip
high power
wireless transmission
power reduction
real time
digital signal processing
power dissipation
low power consumption
vlsi architecture
cmos technology
logic circuits
vlsi circuits
gate array
ultra low power
power saving
image sensor