Shi-Yu Huang

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 53

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ATS

ITC

IEEE Des. Test

Publications

Shu-Yu Chang, Shi-Yu Huang
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop. IEEE Trans. Very Large Scale Integr. Syst. 32 (7) (2024)
Ching-Yi Wen, Shi-Yu Huang
Instant Test and Repair for TSVs using Differential Signaling. J. Electron. Test. 40 (2) (2024)
Cheng-Wen Wu, Shi-Yu Huang
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. ETS (2024)
Shun-Hua Yang, Shi-Yu Huang
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme. J. Electron. Test. 40 (1) (2024)
Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang
Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL. MWSCAS (2023)
Lin Liu, Lai Chi, Shi-Yu Huang, Ka-Yi Yeh
Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. CoRR (2023)
Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. FPL (2023)
Chen-Lin Tsai, Shi-Yu Huang
Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test. ITC-Asia (2023)
Ont-Derh Lin, Shi-Yu Huang
Cell-Based Aging Sensor Using Built-In Speed Grading. NorCAS (2023)
Yung-Chuan Su, Shi-Yu Huang
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. ITC-Asia (2023)
Yung-Chuan Su, Shi-Yu Huang
A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells. IEEE Trans. Very Large Scale Integr. Syst. 31 (3) (2023)
Jun-Yu Yang, Shi-Yu Huang
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Scott Hauck, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark S. Neubauer, Isobel Ojalvo, Savannah Thais, Matthew Trahms
Graph Neural Networks for Charged Particle Tracking on FPGAs. Frontiers Big Data 5 (2022)
Yung-Chuan Su, Shi-Yu Huang
Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter. ISOCC (2022)
Jun-Yu Yang, Shi-Yu Huang
Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Wei-Hao Chen, Shi-Yu Huang
On-Chip Jitter Learning for PLL. IEEE Des. Test 39 (4) (2022)
Chen-Lin Tsai, Shi-Yu Huang
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. ITC (2022)
Wei Chu, Shi-Yu Huang
Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Yi-Hsuan Lee, Shi-Yu Huang
Rigorous Test Flow for PLL to Identify Weak Devices. ITC-Asia (2021)
Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark Neubauer, Isobel Ojalvo, Savannah Thais
Graph Neural Networks for Charged Particle Tracking on FPGAs. CoRR (2021)
Chen-Lin Tsai, Wei-Hao Chen, Shi-Yu Huang
A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal. ITC-Asia (2021)
Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. ITC (2020)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Wei Chu, Wei-Hao Chen, Shi-Yu Huang
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. ICCD (2020)
Derek Lin, Jun-Yu Yang, Shi-Yu Huang
A Voting Phase Detector Design with Mitigated Process Variation. ISOCC (2020)
Jun-Yu Yang, Shi-Yu Huang
Fault and Soft Error Tolerant Delay-Locked Loop. ATS (2020)
Chia-Hua Wu, Shi-Yu Huang, Yung-Fa Chou, Ding-Ming Kwai
Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Des. Test 37 (4) (2020)
Shi-Yu Huang
Overview of On-Chip Performance Monitors for Clock Signals. ATS (2020)
Wei Chu, Shi-Yu Huang
Online Testing of Clock Delay Faults in a Clock Network. ITC-Asia (2019)
Wei Chu, Shi-Yu Huang
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. ITC (2019)
Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang
A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop. IEEE Access 7 (2019)
Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC (2019)
Guan-Hao Lian, Wei-yi Chen, Shi-Yu Huang
Cloud-Based Online Ageing Monitoring for IoT Devices. IEEE Access 7 (2019)
Wei Chu, Shi-Yu Huang
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling. NEWCAS (2019)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC (2019)
Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. DAC (2019)
Yu-Chi Wei, Shi-Yu Huang
A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL. ISOCC (2018)
Cheng-En Lee, Shi-Yu Huang
A Cell-Based Fractional-N Phase-Locked Loop Compiler. SMACD (2018)
Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
DLL-Assisted Clock Synchronization Method for Multi-Die ICs. ICCD (2017)
Shi-Yu Huang
Test strategies for the clock and power distribution networks in a multi-die IC. VLSI-DAT (2017)
Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai
Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI (2017)
Guan-Hao Lian, Shi-Yu Huang, Wei-yi Chen
Cloud-Based PVT Monitoring System for IoT Devices. ATS (2017)
Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS (2016)
Shi-Yu Huang, Chih-Chieh Zheng
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs. ATS (2016)
Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Testing of small delay faults in a clock network. ETS (2016)
Pei-Ching Huang, Shi-Yu Huang
Cell-based delay locked loop compiler. ISOCC (2016)
Shi-Yu Huang
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects. ATS (2016)
Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33 (6) (2016)
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33 (2) (2016)
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
Online slack-time binning for IO-registered die-to-die interconnects. ITC (2016)
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE (2015)
Jinn-Yann Liu, Shi-Yu Huang, Ta-Shun Chu
Cell-based programmable phase shifter design for pulsed radar SoC. ASICON (2015)
Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 20 (2) (2015)
Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
Temperature-aware online testing of power-delivery TSVs. 3DIC (2015)
Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Monitoring the delay of long interconnects via distributed TDC. ITC (2015)
Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS (2014)
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Shi-Yu Huang, Li-Ren Huang
PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning. IEEE Des. Test 31 (4) (2014)
Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS (2014)
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS (2013)
Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
Worst-case IR-drop monitoring with 1GHz sampling rate. VLSI-DAT (2013)
Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC (2013)
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
Mid-bond Interposer Wire Test. Asian Test Symposium (2013)
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng
Cell-Based Process Resilient Multiphase Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
A unified method for parametric fault characterization of post-bond TSVs. ITC (2012)
Feng-Cheng Huang, Shi-Yu Huang, Ji-Wei Ker, Yung-Chang Chen
High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. IEEE Trans. Circuits Syst. Video Technol. 22 (3) (2012)
Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
A UWB IR timed-array radar using time-shifted direct-sampling architecture. VLSIC (2012)
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. VLSI-DAT (2012)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Programmable Leakage Test and Binning for TSVs. Asian Test Symposium (2012)
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Small delay testing for TSVs in 3-D ICs. DAC (2012)
Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Des. Test Comput. 28 (4) (2011)
Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC (2011)
Cheng-Hung Lo, Shi-Yu Huang
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. IEEE J. Solid State Circuits 46 (3) (2011)
Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao
A fully cell-based design for timing measurement of memory. ITC (2011)
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC (2011)
Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen
Black-box leakage power modeling for cell library and SRAM compiler. DATE (2011)
Bor-Woei Kuo, Hsun-Hao Chang, Yung-Chang Chen, Shi-Yu Huang
A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map. J. Robotics 2011 (2011)
Hsuan-Jung Hsu, Shi-Yu Huang
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium (2010)
Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee
Power aware SID-based simulator for embedded multicore DSP subsystems. CODES+ISSS (2010)
Chao-Wen Tzeng, Shi-Yu Huang
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT (2010)
Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang
PAC duo system power estimation at ESL. ASP-DAC (2010)
Chao-Wen Tzeng, Shi-Yu Huang
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu
-Tuning Scheme With Speed-Margining for Low-Power SRAM. IEEE J. Solid State Circuits 44 (10) (2009)
Chao-Wen Tzeng, Shi-Yu Huang
QC-Fill: An X-Fill method for quick-and-cool scan test. DATE (2009)

Shi-Yu Huang.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Shi-Yu Huang