Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.
Yu-Hsiang LinShi-Yu HuangKun-Han TsaiWu-Tung ChengStephen K. SunterYung-Fa ChouDing-Ming KwaiPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)