Wu-Tung Cheng

ORCID

Publication Activity (10 Years)

Years Active: 1985-2022
Publications (10 Years): 29

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ATS

ITC

ETS

Publications

Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson
Industry Evaluation of Reversible Scan Chain Diagnosis. ITC (2022)
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS (2022)
Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. ATS (2021)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige
Diagnosis and Yield Learning. ITC-Asia (2021)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia (2020)
Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. ITC-Asia (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37 (4) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS (2019)
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS (2019)
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma, Fengju Niu, Junna Zhong, Wen-Lung Hsu
Reversible Scan Based Diagnostic Patterns. VLSI-DAT (2019)
Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy
A supervised machine learning application in volume diagnosis. ETS (2019)
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
Deep Learning Based Test Compression Analyzer. ATS (2019)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC (2019)
Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng
Scan Chain Diagnosis Based on Unsupervised Machine Learning. ATS (2017)
Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy
Volume diagnosis data mining. ETS (2017)
Yu Huang, Wu-Tung Cheng
On designing two-dimensional scan architecture for test chips. VLSI-DAT (2017)
Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS (2017)
Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS (2016)
Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS (2016)
Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Testing of small delay faults in a clock network. ETS (2016)
Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33 (6) (2016)
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33 (2) (2016)
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
Online slack-time binning for IO-registered die-to-die interconnects. ITC (2016)
Wu-Tung Cheng, Sudhakar M. Reddy
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. VLSI Design (2015)
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE (2015)
Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke
Diagnosing timing related cell internal defects for FinFET technology. VLSI-DAT (2015)
Yu Huang, Wu Yang, Wu-Tung Cheng
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. ETS (2015)
Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng
A test-application-count based learning technique for test time reduction. VLSI-DAT (2015)
Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS (2015)
Wu-Tung Cheng
Identify problematic layout patterns through volume diagnosis. VLSI-DAT (2015)
Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Monitoring the delay of long interconnects via distributed TDC. ITC (2015)
Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS (2014)
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS (2014)
Huaxing Tang, Brady Benware, Michael Reese, Joseph Caroselli, Thomas Herrmann, Friedrich Hapke, Robert Tao, Wu-Tung Cheng, Manish Sharma
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models. ATS (2014)
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW (2014)
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS (2013)
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
EDT bandwidth management - Practical scenarios for large SoC designs. ITC (2013)
Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC (2013)
Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC (2013)
Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
Distributed dynamic partitioning based diagnosis of scan chain. VTS (2013)
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
Mid-bond Interposer Wire Test. Asian Test Symposium (2013)
Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng
Improve speed path identification with suspect path expressions. VLSI-DAT (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
A unified method for parametric fault characterization of post-bond TSVs. ITC (2012)
Wu-Tung Cheng, Feng-Ming Kuo
Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis. Asian Test Symposium (2012)
Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang
Scan-Based Speed-Path Debug for a Microprocessor. IEEE Des. Test Comput. 29 (4) (2012)
Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium (2012)
Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia
A Hybrid Flow for Memory Failure Bitmap Classification. Asian Test Symposium (2012)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
Programmable Leakage Test and Binning for TSVs. Asian Test Symposium (2012)
Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
Improved volume diagnosis throughput using dynamic design partitioning. ITC (2012)
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Small delay testing for TSVs in 3-D ICs. DAC (2012)
Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT (2011)
Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC (2011)
Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng
Deterministic IDDQ diagnosis using a net activation based model. ITC (2011)
Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware
On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium (2011)
Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
Case study of scan chain diagnosis and PFA on a low yield wafer. ITC (2010)
Wu-Tung Cheng, Yu Huang
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. Asian Test Symposium (2010)
Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor
Emulating and diagnosing IR-drop by using dynamic SDF. ASP-DAC (2010)
Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
Full-circuit SPICE simulation based validation of dynamic delay estimation. ETS (2010)
Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD (2010)
Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy
Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium (2010)
Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC (2010)
Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz
Scan based speed-path debug for a microprocessor. ETS (2010)
Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
Test cycle power optimization for scan-based designs. ITC (2010)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium (2009)
Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium (2009)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. Asian Test Symposium (2009)
Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai
Speed-Path Debug Using At-Speed Scan Test Patterns. ETS (2009)
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy
Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE (2009)
Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. ITC (2008)
Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC (2008)
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
Detection and Diagnosis of Static Scan Cell Internal Defect. ITC (2008)
Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
Automatic Test Pattern Generation for Interconnect Open Defects. VTS (2008)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo
Diagnose Multiple Stuck-at Scan Chain Faults. ETS (2008)
Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. 25 (3) (2008)
Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake
Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS (2008)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
Reducing Scan Shift Power at RTL. VTS (2008)
Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
A Robust Automated Scan Pattern Mismatch Debugger. ATS (2008)
Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma
Hyperactive Faults Dictionary to Increase Diagnosis Throughput. ATS (2008)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
Fault Dictionary Based Scan Chain Failure Diagnosis. ATS (2007)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann
Diagnose compound scan chain and system logic defects. ITC (2007)
Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich
A RTL Testability Analyzer Based on Logical Virtual Prototyping. ATS (2007)
Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg
Scan Diagnosis and Its Successful Industrial Applications. ATS (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Wu-Tung Cheng