Circuit and Methodology for Testing Small Delay Faults in the Clock Network.
Shaofu YangZhi-Yuan WenShi-Yu HuangKun-Han TsaiWu-Tung ChengPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
Keyphrases
- high speed
- test cases
- network structure
- network model
- peer to peer
- wireless sensor networks
- end to end
- complex networks
- duty cycle
- computer networks
- fault model
- network management
- abnormal events
- asynchronous transfer mode
- analog circuits
- circuit design
- network resources
- communication networks
- network traffic
- fault diagnosis