Ting-Chi Wang

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 33

Top Topics

Reverse Engineer

Convolutional Neural Network

Highly Redundant

Pattern Classification

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Zi-Hao Guo, Ting-Chi Wang
SMT-Based Layout Synthesis Approaches for Quantum Circuits. ISPD (2024)
Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
An Effective Netlist Planning Approach for Double-sided Signal Routing. ASPDAC (2024)
Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE (2024)
Ting-Chi Wang
Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design. ISPD (2024)
Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang
A Fast and Robust Global Router with Capacity Reduction Techniques. ASPDAC (2024)
Fang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang
A Bounding Box-based Net Partitioning Method for Double-sided Routing. ACM Great Lakes Symposium on VLSI (2024)
Chieh-Yu Cheng, Ting-Chi Wang
Routability-aware Placement Guidance Generation for Mixed-size Designs. ISQED (2023)
Chun-Wei Chiu, Yun-Kai Fang, Shao-Ting Chung, Ting-Chi Wang
A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints. ACM Great Lakes Symposium on VLSI (2023)
Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak, Ting-Chi Wang
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. ACM Great Lakes Symposium on VLSI (2023)
Zhi-Hong Lee, Chen-Han Lu, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen
A Robust Routing Guide Generation Approach for Mixed-Size Designs. MLCAD (2023)
Po-Hao Huang, Yung-Yuan Lan, Wilbert Harriman, Venesia Chiuwanara, Ting-Chi Wang
Fast and Accurate Detection of Audio Adversarial Examples. ISCAS (2023)
Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang
Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. ICCAD (2022)
Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. VLSI-SoC (2022)
Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang
HybridGP: Global Placement for Hybrid-Row-Height Designs. ASP-DAC (2022)
Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Kuei-Huan Chang, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen
On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network. ISQED (2022)
Po-Hao Huang, Honggang Yu, Max Panoff, Ting-Chi Wang
Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders. ACM J. Emerg. Technol. Comput. Syst. 18 (3) (2022)
Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC (2022)
Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. ISPD (2021)
Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE (2020)
Kuei-Huan Chang, Po-Hao Huang, Honggang Yu, Yier Jin, Ting-Chi Wang
. ASP-DAC (2020)
Da-Yu Kao, Ting-Chi Wang, Fu-Ching Tsai
Forensic Artifacts of Network Traffic on WeChat Calls. ICACT (2020)
Sheng-Hao Wang, Yen-Jong Chen, Ting-Chi Wang, Oscar Chen
An Algorithm for Rule-based Layout Pattern Matching. ICCAD (2020)
Weida Zhu, Xinghai Zhang, Genggeng Liu, Wenzhong Guo, Ting-Chi Wang
MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router. VLSI-DAT (2020)
Yi-Cheng Zhao, Yu-Chieh Lin, Ting-Chi Wang, Ting-Hsiung Wang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao
. DATE (2019)
Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang
RDTA: An Efficient Routability-Driven Track Assignment Algorithm. ACM Great Lakes Symposium on VLSI (2019)
Yu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang
A practical detailed placement algorithm under multi-cell spacing constraints. ICCAD (2018)
Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI (2018)
Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi
A routing framework for technology migration with bump encroachment. Integr. 58 (2017)
Ye-Hong Chen, Sheng-He Wang, Ting-Chi Wang
On refining standard cell placement for self-aligned double patterning. DATE (2017)
Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
Delay-driven layer assignment for advanced technology nodes. ASP-DAC (2017)
Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang
Negotiation-based track assignment considering local nets. ASP-DAC (2016)
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
Online slack-time binning for IO-registered die-to-die interconnects. ITC (2016)
Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. ISPD (2015)
Hsi-An Chien, Ye-Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang
On Refining Row-Based Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI (2014)
Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. ICCAD (2014)
Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
A study on unroutable placement recognition. ISPD (2014)
Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang
. DATE (2014)
Chih-Hung Liu, Chun-Xun Lin, I-Che Chen, D. T. Lee, Ting-Chi Wang
Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. DAC (2014)
Hsi-An Chien, Ting-Chi Wang
Redundant-via-aware ECO routing. ASP-DAC (2014)
Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. DATE (2014)
Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang
Density-aware Detailed Placement with Instant Legalization. DAC (2014)
Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC (2013)
Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang
Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC (2011)
Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang
An enhanced global router with consideration of general layer directives. ISPD (2011)
Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang
Through-Silicon Via Planning in 3-D Floorplanning. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Tsung-Hsien Lee, Ting-Chi Wang
Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. ICCAD (2010)
Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI (2010)
Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang
GLADE: A modern global router considering layer directives. ICCAD (2010)
Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang
Enhanced Double Via Insertion Using Wire Bending. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
NTHU-Route 2.0: A Robust Global Router for Modern Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
Pad assignment for die-stacking System-in-Package design. ICCAD (2009)
Tsung-Hsien Lee, Ting-Chi Wang
Robust layer assignment for via optimization in multi-layer global routing. ISPD (2009)
Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang
Redundant via insertion with wire bending. ISPD (2009)
Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang
An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC (2008)
Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
A new global router for modern designs. ASP-DAC (2008)
Tien-Yuan Hsu, Ting-Chi Wang
A generalized network flow based algorithm for power-aware FPGA memory mapping. DAC (2008)
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
Optimal post-routing redundant via insertion. ISPD (2008)
Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang
NTHU-Route 2.0: a fast and stable global router. ICCAD (2008)
Tien-Ting Fang, Ting-Chi Wang
Fast Buffered Delay Estimation Considering Process Variations. ASP-DAC (2007)
Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC (2007)
Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. ASP-DAC (2007)
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
Post-routing redundant via insertion and line end extension with via density consideration. ICCAD (2006)
Kuang-Yao Lee, Ting-Chi Wang
Post-routing redundant via insertion for yield/reliability improvement. ASP-DAC (2006)
Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang
Maze routing with OPC consideration. ASP-DAC (2005)
Zhong-Ching Lu, Ting-Chi Wang
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. ASP-DAC (2005)
Hao-Yueh Hsieh, Ting-Chi Wang
Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. ISCAS (2) (2005)
Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (7) (2004)
Cliff C. N. Sze, Ting-Chi Wang
Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Chin Ngai Sze, Ting-Chi Wang
Performance-driven multi-level clustering for combinational circuits. ASP-DAC (2003)
Cliff C. N. Sze, Ting-Chi Wang
Multi-Level Circuit Clustering for Delay Minimization. IWLS (2002)
S. Dhamdhere, Ningyu Zhou, Ting-Chi Wang
Module placement with pre-placed modules using the corner block list representation. ISCAS (1) (2002)
Cliff C. N. Sze, Ting-Chi Wang
Optimal circuit clustering with variable interconnect delay. ISCAS (4) (2002)
Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang
Module placement with boundary constraints using the sequence-pair representation. ASP-DAC (2001)
Yi-He Jiang, Jianbang Lai, Ting-Chi Wang
Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) (2001)
En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang
Slicing floorplan design with boundary-constrained modules. ISPD (2001)
Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang
Power minization in LUT-based FPGA technology mapping. ASP-DAC (2001)
Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium (2000)
En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang
On accelerating slicing floorplan design with boundary constraints. ISCAS (2000)
Hsun-Cheng Lee, Ting-Chi Wang
Feasible two-way circuit partitioning with complex resource constraints. ASP-DAC (2000)
Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
Faster and Better Spectral Algorithms for Multi-Way Partitioning. ASP-DAC (1999)
Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (1) (1997)
T. W. Her, Ting-Chi Wang, Martin D. F. Wong
Performance-driven channel pin assignment algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (7) (1995)
Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
Optimal net assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (2) (1995)
Ting-Chi Wang, D. F. Wong, Yachyang Sun, C. K. Wong
On over-the-cell channel routing. EURO-DAC (1993)
Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
Routing for symmetric FPGAs and FPICs. ICCAD (1993)
Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
A Graph Partitioning Problem for Multiple-chip Design. ISCAS (1993)
Ting-Chi Wang, D. F. Wong
Graph-based techniques to speed up floorplan area optimization. Integr. 15 (2) (1993)
Ting-Chi Wang, Martin D. F. Wong
Optimal floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (8) (1992)
Ting-Chi Wang, D. F. Wong
A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC (1992)
Ting-Chi Wang, D. F. Wong
Efficient shape curve construction in floorplan design. EURO-DAC (1991)
Ting-Chi Wang, D. F. Wong
An Optimal Algorithm for Floorplan Area Optimization. DAC (1990)