Yung-Chia Lin

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 3

Top Topics

Optimization Problems

Complex Systems

Top Venues

J. Signal Process. Syst.

Publications

Kuan-Hsun Chen, Yung-Chia Lin, Jenq-Kuen Lee
Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications. J. Signal Process. Syst. 95 (5) (2023)
Chia-Hsuan Chang, Chun-Chieh Yang, Jenq-Kuen Lee, Yung-Chia Lin
Case Study: Support OpenCL Complex Class for Baseband Computing. IWOCL (2019)
Yung-Chia Lin, Jenq-Kuen Lee, François Bodin
Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization. J. Signal Process. Syst. 91 (3-4) (2019)
Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurr. Comput. Pract. Exp. 21 (1) (2009)
Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang
An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC (2008)
Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. J. Signal Process. Syst. 51 (3) (2008)
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. J. Signal Process. Syst. 51 (3) (2008)
Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee
PALF: compiler supports for irregular register files in clustered VLIW DSP processors. Concurr. Comput. Pract. Exp. 19 (18) (2007)
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. J. Supercomput. 42 (2) (2007)
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. RTCSA (2006)
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee
Compiler Supports and Optimizations for PAC VLIW DSP Processors. LCPC (2005)
Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
System-level design space exploration for security processor prototyping in analytical approaches. ASP-DAC (2005)
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC (2004)
Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee
Compiler Optimizations with DSP-Specific Semantic Descriptions. LCPC (2002)