TingTing Hwang

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 15

Top Venues

DATE

ASP-DAC

IEEE Trans. Very Large Scale Integr. Syst.

SoCC

Publications

Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE (2024)
Yuan-Tai Lin, Chin-Yu Sun, TingTing Hwang
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties. SOCC (2023)
RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang
Expanding In-Cone Obfuscated Tree for Anti SAT Attack. DATE (2023)
Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. 94 (2021)
Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC (2021)
Chin-Yu Sun, Hsiao-Ling Wu, Hung-Min Sun, TingTing Hwang
A New Attack for Self-Certified Digital Signatures for E-commerce Applications. J. Inf. Sci. Eng. 37 (6) (2021)
Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC (2019)
Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC (2019)
Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR (2019)
Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang
Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs. ASP-DAC (2017)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang
Architectural evaluations on TSV redundancy for reliability enhancement. DATE (2017)
Wei-Hen Lo, Kai-zen Liang, TingTing Hwang
Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). DATE (2016)
Wei-Hen Lo, Kang Chi, TingTing Hwang
Architecture of Ring-Based Redundant TSV for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE (2016)
Wei-Hen Lo, Kang Chi, TingTing Hwang
Architecture of ring-based redundant TSV for clustered faults. DATE (2015)
Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang
Fault-tolerant TSV by using scan-chain test TSV. ASP-DAC (2014)
Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang
Utilizing Circuit Structure for Scan Chain Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Fu-Wei Chen, TingTing Hwang
Clock-Tree Synthesis with Methodology of Reuse in 3D-IC. ACM J. Emerg. Technol. Comput. Syst. 10 (3) (2014)
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang
Compaction-free compressed cache for high performance multi-core system. ICCAD (2014)
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
Stacking signal TSV for thermal dissipation in global routing for 3D IC. ASP-DAC (2013)
Po-Yang Hsu, TingTing Hwang
Thread-criticality aware dynamic cache reconfiguration in multi-core system. ICCAD (2013)
Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang
Utilizing circuit structure for scan chain diagnosis. ETS (2013)
Ang-Chih Hsieh, TingTing Hwang
Thermal-aware memory mapping in 3D designs. ACM Trans. Embed. Comput. Syst. 13 (1) (2013)
Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 20 (12) (2012)
Ang-Chih Hsieh, TingTing Hwang
Run-Time Reconfiguration of Expandable Cache for Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Ang-Chih Hsieh, TingTing Hwang
TSV Redundancy: Architecture and Design Issues in 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Fu-Wei Chen, TingTing Hwang
Clock tree synthesis with methodology of re-use in 3D IC. DAC (2012)
Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. ASP-DAC (2011)
Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang
A physical-location-aware fault redistribution for maximum IR-drop reduction. ASP-DAC (2011)
Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang
A new architecture for power network in 3D IC. DATE (2011)
Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. ICPP (2011)
Wen-Wen Hsieh, S.-L. Chen, I-Sheng Lin, TingTing Hwang
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
TSV redundancy: Architecture and design issues in 3D IC. DATE (2010)
Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin
Randomness Enhancement Using Digitalized Modified Logistic Map. IEEE Trans. Circuits Syst. II Express Briefs (12) (2010)
Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. IEEE Trans. Very Large Scale Integr. Syst. 18 (12) (2010)
Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin
A Fast Digital Chaotic Generator for Secure Communication. Int. J. Bifurc. Chaos 20 (12) (2010)
Wen-Wen Hsieh, TingTing Hwang
Thermal-aware post compilation for VLIW architectures. ASP-DAC (2009)
Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang
New spare cell design for IR drop minimization in Engineering Change Order. DAC (2009)
Ang-Chih Hsieh, TingTing Hwang
Thermal-aware memory mapping in 3D designs. DATE (2009)
Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. DATE (2009)
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang
Transition-aware decoupling-capacitor allocation in power noise reduction. ICCAD (2008)
Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang
Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13 (1) (2008)
Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang
Digital Secure-Communication Using Robust Hyper-Chaotic Systems. Int. J. Bifurc. Chaos 18 (11) (2008)
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
Skew aware polarity assignment in clock tree. ICCAD (2007)
Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. ACM Trans. Design Autom. Electr. Syst. 12 (3) (2007)
Yi-Yu Liu, TingTing Hwang
Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. J. Supercomput. 42 (2) (2007)
Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (12) (2007)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Yi-Yu Liu, TingTing Hwang
Crosstalk-aware domino logic synthesis. DATE (2006)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11 (4) (2006)
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
Performance-driven crosstalk elimination at post-compiler level. ISCAS (2006)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11 (4) (2006)
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
Switching-activity driven gate sizing and Vth assignment for low power design. ASP-DAC (2006)
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
A bus architecture for crosstalk elimination in high performance processor design. CODES+ISSS (2006)
Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang
Instruction buffering for nested loops in low-power design. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
Low-power techniques for network security processors. ASP-DAC (2005)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) (2005)
Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu
Functionality directed clustering for low power MTCMOS design. ASP-DAC (2005)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
Decomposition of Instruction Decoder for Low Power Design. DATE (2004)
Chi-Wei Hu, TingTing Hwang
Output-pattern directed decomposition for low power design. ISCAS (5) (2004)
Yen-Te Ho, TingTing Hwang
Low power design using dual threshold voltage. ASP-DAC (2004)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
Crosstalk Minimization in Logic Synthesis for PLA. DATE (2004)
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC (2004)
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE (2003)
Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE (2003)
MingHung Lee, TingTing Hwang, Shi-Yu Huang
Decomposition of Extended Finite State Machine for Low Power Design. DATE (2003)
Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Design Autom. Electr. Syst. 8 (2) (2003)
Shih-Liang Chen, TingTing Hwang, C. L. Liu
A technology mapping algorithm for CPLD architectures. FPT (2002)
Chi Ta Wu, TingTing Hwang
Instruction buffering for nested loops in low power design. ISCAS (4) (2002)
Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7 (2) (2002)
LiYi Lin, Yi-Yu Liu, TingTing Hwang
A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC (2001)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
Binary decision diagram with minimum expected path length. DATE (2001)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
Compiler Optimization on Instruction Scheduling for Low Power. ISSS (2000)
Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang
A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. ASP-DAC (1999)
How-Rern Lin, TingTing Hwang
On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
Logic Transformation for Low Power Synthesis. DATE (1999)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Architecture driven circuit partitioning. ICCAD (1998)
Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang
A Re-engineering Approach to Low Power FPGA Design Using SPFD. DAC (1998)
Chau-Shen Chen, TingTing Hwang
Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electron. Test. 13 (1) (1998)
Kuo-Hua Wang, TingTing Hwang
Boolean matching for incompletely specified functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (2) (1997)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Low Power FPGA Design - A Re-engineering Approach. DAC (1997)
Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (3) (1997)
Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1 (3) (1996)
Kuo-Hua Wang, TingTing Hwang, Cheng Chen
Exploiting communication complexity for Boolean matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (10) (1996)
How-Rern Lin, Yu-Chin Hsu, TingTing Hwang
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31 (5) (1996)
Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang
Layout Driven Selecting and Chaining of Partial Scan. DAC (1996)
Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (10) (1996)
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
How-Rern Lin, TingTing Hwang
Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC (1995)
Kuo-Hua Wang, TingTing Hwang
Boolean Matching for Incompletely Specified Functions. DAC (1995)
How-Rern Lin, TingTing Hwang
Dynamical identification of critical paths for iterative gate sizing. ICCAD (1994)
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC (1994)
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (2) (1994)

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Publication Activity (10 Years)

Top Topics

Top Venues

TingTing Hwang