Yi-Yu Liu

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 6

Top Topics

Spatial Locality

Reconfigurable Architecture

Simultaneous Optimization

Top Venues

J. Inf. Sci. Eng.

ACM Trans. Design Autom. Electr. Syst.

IEICE Electron. Express

Publications

Jun-Sheng Wu, Chi-An Pan, Yi-Yu Liu
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. IEEE Trans. Computers 70 (9) (2021)
An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. ICCAD (2020)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE (2016)
Po-Yang Hsu, Yi-Yu Liu
Buffer Design and Assignment for Structured ASIC. J. Inf. Sci. Eng. 30 (1) (2014)
Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu
Hybrid LUT and SOP Reconfigurable Architecture. J. Inf. Sci. Eng. 30 (1) (2014)
Ting-Wei Hung, Yen-Hao Chen, Yi-Yu Liu
Memory management for dual-addressing memory architecture. IEICE Electron. Express 10 (15) (2013)
Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu
Routability optimization for crossbar-switch structured ASIC design. ACM Trans. Design Autom. Electr. Syst. 18 (3) (2013)
Yen-Hao Chen, Yi-Yu Liu
Dual-addressing memory architecture for two-dimensional memory access patterns. DATE (2013)
Hsiang-Yuan Yeh, Yi-Yu Liu, Cheng-Yu Yeh, Von-Wun Soo
Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search. BIBE (2010)
Fu-Wei Chen, Yi-Yu Liu
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
Buffer design and optimization for lut-based structured ASIC design styles. ACM Great Lakes Symposium on VLSI (2009)
Fu-Wei Chen, Yi-Yu Liu
Performance-driven dual-rail insertion for chip-level pre-fabricated design. DATE (2009)
Fu-Wei Chen, Yi-Yu Liu
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. DATE (2008)
Yi-Yu Liu, TingTing Hwang
Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Yi-Yu Liu, TingTing Hwang
Crosstalk-aware domino logic synthesis. DATE (2006)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11 (4) (2006)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
Crosstalk Minimization in Logic Synthesis for PLA. DATE (2004)
LiYi Lin, Yi-Yu Liu, TingTing Hwang
A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC (2001)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
Binary decision diagram with minimum expected path length. DATE (2001)