C. L. Liu

Publication Activity (10 Years)

Years Active: 1964-2012
Publications (10 Years): 0

Top Venues

ISPD

Publications

C. L. Liu
I attended the nineteenth design automation conference. ISPD (2012)
C. L. Liu
The High Walls have Crumpled. VLSI Design (2005)
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11 (1) (2003)
Ali Pinar, C. L. Liu
Compacting sequences with invariant transition frequencies. ACM Trans. Design Autom. Electr. Syst. 8 (2) (2003)
Ki-Seok Chung, Taewhan Kim, C. L. Liu
A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. 11 (2) (2002)
Shih-Liang Chen, TingTing Hwang, C. L. Liu
A technology mapping algorithm for CPLD architectures. FPT (2002)
Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu
Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. 31 (3) (2002)
S. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C. W. Tsai, T. B. Wu, Rich Liu
Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. CICC (2002)
Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7 (2) (2002)
Prashant Saxena, C. L. Liu
Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Ki-Seok Chung, Taewhan Kim, C. L. Liu
G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. 27 (3) (2001)
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
Binary decision diagram with minimum expected path length. DATE (2001)
Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC (2001)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Junhyung Um, Taewhan Kim, C. L. Liu
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC (2000)
Prashant Saxena, C. L. Liu
A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (6) (2000)
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
Noise-aware power optimization for on-chip interconnect. ISLPED (2000)
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD (2000)
Chaeryung Park, Taewhan Kim, C. L. Liu
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design 2000 (4) (2000)
C. L. Liu
From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. RTSS (1999)
Junhyung Um, Taewhan Kim, C. L. Liu
Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD (1999)
Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
Implication graph based domino logic synthesis. ICCAD (1999)
Chaeryung Park, Taewhan Park, C. L. Liu
An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) (1999)
Prashant Saxena, Peichen Pan, C. L. Liu
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design (1999)
Peichen Pan, C. L. Liu
Partial Scan with Preselected Scan Signals. IEEE Trans. Computers 48 (9) (1999)
Prashant Saxena, C. L. Liu
Crosstalk Minimization Using Wire Perturbations. DAC (1999)
Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
Logic Transformation for Low Power Synthesis. DATE (1999)
Ali Pinar, C. L. Liu
Power invariant vector sequence compaction. ICCAD (1998)
Ki-Seok Chung, C. L. Liu
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED (1998)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Architecture driven circuit partitioning. ICCAD (1998)
Chaeryung Park, Taewhan Kim, C. L. Liu
Register Allocation - A Hierarchical Reduction Approach. J. VLSI Signal Process. 19 (3) (1998)
Peichen Pan, Arvind K. Karandikar, C. L. Liu
Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (6) (1998)
Prashant Saxena, C. L. Liu
A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD (1998)
Unni Narayanan, Peichen Pan, C. L. Liu
Low power logic synthesis under a general delay model. ISLPED (1998)
Peichen Pan, C. L. Liu
Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (1) (1997)
Anmol Mathur, C. L. Liu
Timing-driven placement for regular architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (6) (1997)
Arvind K. Karandikar, Peichen Pan, C. L. Liu
Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD (1997)
Peichen Pan, Sai-keung Dong, C. L. Liu
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica 18 (4) (1997)
Unni Narayanan, C. L. Liu
Low power logic synthesis for XOR based circuits. ICCAD (1997)
Chau-Shen Chen, TingTing Hwang, C. L. Liu
Low Power FPGA Design - A Re-engineering Approach. DAC (1997)
Peichen Pan, Weiping Shi, C. L. Liu
Area Minimization for Hierarchical Floorplans. Algorithmica 15 (6) (1996)
Srilata Raman, C. L. Liu, Larry G. Jones
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. VLSI Design 4 (4) (1996)
Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I (1996)
Srilata Raman, C. L. Liu, Larry G. Jones
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. ED&TC (1996)
Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1 (3) (1996)
Peichen Pan, C. L. Liu
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC (1996)
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
An algorithm for synthesis of system-level interface circuits. ICCAD (1996)
Peichen Pan, C. L. Liu
Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA (1996)
Taewhan Kim, C. L. Liu
An integrated algorithm for incremental data path synthesis. J. VLSI Signal Process. 12 (3) (1996)
Tong Gao, C. L. Liu
Minimum crosstalk channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (5) (1996)
Anmol Mathur, C. L. Liu
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. ED&TC (1996)
Xiangfeng Chen, Peichen Pan, C. L. Liu
Desensitization for Power Reduction in Sequential Circuits. DAC (1996)
Anmol Mathur, K. C. Chen, C. L. Liu
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA (1995)
Tong Gao, C. L. Liu
Minimum crosstalk switchbox routing. Integr. 19 (3) (1995)
Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. IEEE Trans. Parallel Distributed Syst. 6 (5) (1995)
Peichen Pan, C. L. Liu
Area minimization for floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (1) (1995)
Taewhan Kim, C. L. Liu
A new approach to the multiport memory allocation problem in data path synthesis. Integr. 19 (3) (1995)
Peichen Pan, C. L. Liu
Partial Scan with Pre-selected Scan Signals. DAC (1995)
Anmol Mathur, K. C. Chen, C. L. Liu
Re-engineering of timing constrained placements for regular architectures. ICCAD (1995)
Peichen Pan, Weiping Shi, C. L. Liu
Area minimization for hierarchical floorplans. ICCAD (1994)
Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Yachyang Sun, C. L. Liu
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. DAC (1994)
Srilata Raman, C. L. Liu, Larry G. Jones
A delay driven FPGA placement algorithm. EURO-DAC (1994)
Tong Gao, C. L. Liu
Minimum crosstalk switchbox routing. ICCAD (1994)
Anmol Mathur, C. L. Liu
Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD (1994)
Jason Cong, Bryan Preas, C. L. Liu
Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (5) (1993)
Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
Routing for symmetric FPGAs and FPICs. ICCAD (1993)
Wei-Kuan Shih, Jane W.-S. Liu, C. L. Liu
Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. IEEE Trans. Software Eng. 19 (12) (1993)
Tong Gao, C. L. Liu
Minimum crosstalk channel routing. ICCAD (1993)
Chaeryung Park, Taewhan Kim, C. L. Liu
Register allocation for data flow graphs with conditional branches and loops. EURO-DAC (1993)
Peichen Pan, Sai-keung Dong, C. L. Liu
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC (1993)
Taewhan Kim, C. L. Liu
Utilization of Multiport Memories in Data Path Synthesis. DAC (1993)
Tong Gao, Pravin M. Vaidya, C. L. Liu
A Performance Driven Macro-Cell Placement Algorithm. DAC (1992)
Peichen Pan, C. L. Liu
Area minimization for general floorplans. ICCAD (1992)
C. L. Liu
Fundamentals of Real-Time Scheduling (Extended Abstract). NATO ASI RTC (1992)
Yachyang Sun, C. L. Liu
An Area Minimizer for Floorplans with L-Shaped Regions. ICCD (1992)
Tong Gao, Pravo M. Vaidya, C. L. Liu
A New Performance Driven Placement Algorithm. ICCAD (1991)
Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu
A Channel Router for Single Layer Customization Technology. ICCAD (1991)
Nany Hasan, C. L. Liu
Minimum fault covering in reconfigurable arrays. Integr. 11 (3) (1991)
Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu
Disjoint Covers in Replicated Heterogeneous Arrays. SIAM J. Discret. Math. 4 (2) (1991)
Taewhan Kim, Jane W.-S. Liu, C. L. Liu
A Scheduling Algorithm for Conditional Resource Sharing. ICCAD (1991)
Jason Cong, C. L. Liu
On the k-layer planar subset and topological via minimization problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Xianjin Yao, C. L. Liu
PLA logic minimization by simulated annealing. Integr. 9 (3) (1990)
Xianjin Yao, C. L. Liu
Solution of a module orientation and rotation problem. EURO-DAC (1990)
Jason Cong, C. L. Liu
Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (4) (1990)
Nany Hasan, C. L. Liu
Fault covers in reconfigurable PLAs. FTCS (1990)
Jason Cong, C. L. Liu
On the k-layer planar subset and via minimization problems. EURO-DAC (1990)
Jason Cong, Bryan Preas, C. L. Liu
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC (1990)
Ran Libeskind-Hadas, C. L. Liu
Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. DAC (1989)
Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal
Generalized latin squares I. Discret. Appl. Math. 25 (1-2) (1989)
Thomas R. Mueller, D. F. Wong, C. L. Liu
An enhanced bottom-up algorithm for floorplan design. Integr. 7 (2) (1989)
Sai-keung Dong, Jason Cong, C. L. Liu
Constrained floorplan design for flexible blocks. ICCAD (1989)
Xianjin Yao, Masaaki Yamada, C. L. Liu
A new approach to the pin assignment problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (9) (1989)
D. F. Wong, C. L. Liu
Floorplan Design of VLSI Circuits. Algorithmica 4 (2) (1989)
Jason Cong, Martin D. F. Wong, C. L. Liu
A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (10) (1988)
Nany Hasan, Jason Cong, C. L. Liu
A new formulation of yield enhancement problems for reconfigurable chips. ICCAD (1988)
Nany Hasan, C. L. Liu
Minimum fault coverage in reconfigurable arrays. FTCS (1988)

C. L. Liu.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Venues

C. L. Liu