D. F. Wong

ORCID

Publication Activity (10 Years)

Years Active: 1986-2004
Publications (10 Years): 0

Publications

Hua Xiang, Kai-Yuan Chao, D. F. Wong
An ECO algorithm for eliminating crosstalk violations. ISPD (2004)
Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan
A fast and accurate method for interconnect current calculation. ASP-DAC (2003)
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
Wire type assignment for FPGA routing. FPGA (2003)
John F. Croix, D. F. Wong
Blade and razor: cell and interconnect delay analysis using current-based models. DAC (2003)
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
Floorplanning with power supply noise avoidance. ASP-DAC (2003)
Li-Da Huang, Hung-Ming Chen, D. F. Wong
Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE (2003)
Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8 (1) (2003)
Yongseok Cheon, D. F. Wong
Design hierarchy guided multilevel circuit partitioning. ISPD (2002)
Xiaoping Tang, D. F. Wong
Floorplanning with alignment and performance constraints. DAC (2002)
Seokjin Lee, D. F. Wong
Timing-driven routing for FPGAs based on Lagrangian relaxation. ISPD (2002)
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE (2002)
Hua Xiang, Kai-Yuan Chao, D. F. Wong
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD (2002)
Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
Shaping interconnect for uniform current density. ICCAD (2002)
Hua Xiang, D. F. Wong, Xiaoping Tang
An algorithm for integrated pin assignment and buffer planning. DAC (2002)
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
Maze Routing with Buffer Insertion under Transition Time Constraints. DATE (2002)
Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong
On mask layout partitioning for electron projection lithography. ICCAD (2002)
K. K. Lee, D. F. Wong
Incremental reconfiguration of multi-FPGA systems. FPGA (2002)
Youxin Gao, D. F. Wong
A fast and accurate delay estimation method for buffered interconnects. ASP-DAC (2001)
Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD (2001)
Chris C. N. Chu, D. F. Wong
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6 (3) (2001)
Chris C. N. Chu, D. F. Wong
VLSI Circuit Performance Optimization by Geometric Programming. Ann. Oper. Res. 105 (1-4) (2001)
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
Integrated power supply planning and floorplanning. ASP-DAC (2001)
Minghorng Lai, D. F. Wong
Slicing tree is a complete floorplan representation. DATE (2001)
Xiaoping Tang, D. F. Wong
FAST-SP: a fast algorithm for block placement based on sequence pair. ASP-DAC (2001)
Xiaoping Tang, D. F. Wong
Network flow based buffer planning. Integr. 30 (2) (2001)
Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI (2001)
Hua Xiang, Xiaoping Tang, D. F. Wong
An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD (2001)
Minghorng Lai, D. F. Wong
Memory-efficient interconnect optimization. ASP-DAC (2001)
K. K. Lee, D. F. Wong
LRoute: a delay minimal router for hierarchical CPLDs. FPGA (2001)
Youxin Gao, D. F. Wong
A graph based algorithm for optimal buffer insertion under accurate delay models. DATE (2001)
Ruiqi Tian, Xiaoping Tang, D. F. Wong
Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. ISPD (2001)
Xiaoping Tang, D. F. Wong, Ruiqi Tian
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. DATE (2000)
I-Min Liu, Adnan Aziz, D. F. Wong
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE (2000)
Yao-Wen Chang, Kai Zhu, D. F. Wong
Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Huiqun Liu, Kai Zhu, D. F. Wong
FPGA Partitioning with Complex Resource Constraints. VLSI Design 2000 (3) (2000)
Xiaoping Tang, D. F. Wong
Planning buffer locations by network flows. ISPD (2000)
Ruiqi Tian, D. F. Wong, Robert Boone
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. DAC (2000)
I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD (2000)
Youxin Gao, D. F. Wong
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE (2000)
Hai Zhou, D. F. Wong
Optimal low power X OR gate decomposition. DAC (2000)
Minghorng Lai, D. F. Wong
Maze routing with buffer insertion and wiresizing. DAC (2000)
Wai-Kei Mak, D. F. Wong
A fast hypergraph min-cut algorithm for circuit partitioning. Integr. 30 (1) (2000)
Youxin Gao, D. F. Wong
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC (1999)
Chung-Ping Chen, D. F. Wong
Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC (1999)
Youxin Gao, D. F. Wong
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integr. 27 (2) (1999)
Fung Yu Young, D. F. Wong
Slicing Floorplans with Boundary Constraint. ASP-DAC (1999)
K. K. Lee, D. F. Wong
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ICCD (1999)
I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD (1999)
Jacob White, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong
Advances in transistor timing, simulation, and optimization (tutorial abstract). ICCAD (1999)
Fung Yu Young, D. F. Wong
Slicing floorplans with range constraint. ISPD (1999)
Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC (1999)
Wai-Kei Mak, D. F. Wong
A fast hypergraph minimum cut algorithm. ISCAS (6) (1999)
Huiqun Liu, D. F. Wong
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD (1999)
Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
Integrated floorplanning and interconnect planning. ICCAD (1999)
Huiqun Liu, D. F. Wong
Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA (1999)
Fung Yu Young, Chris C. N. Chu, D. F. Wong
Generation of Universal Series-Parallel Boolean Functions. J. ACM 46 (3) (1999)
Huiqun Liu, D. F. Wong
Integrated partitioning and scheduling for hardware/software co-design. ICCD (1998)
Huiqun Liu, Kai Zhu, D. F. Wong
Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA (1998)
Wai-Kei Mak, D. F. Wong
Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA (1998)
Chris C. N. Chu, D. F. Wong
Greedy wire-sizing is linear time. ISPD (1998)
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD (1998)
Fung Yu Young, D. F. Wong
Slicing floorplans with pre-placed modules. ICCAD (1998)
Madhukar R. Korupolu, K. K. Lee, D. F. Wong
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. DAC (1998)
Kai Zhu, Yao-Wen Chang, D. F. Wong
Timing-driven routing for symmetrical-array-based FPGAs. ICCD (1998)
Huiqun Liu, D. F. Wong
Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD (1998)
Chris C. N. Chu, D. F. Wong
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE (1998)
Hai Zhou, D. F. Wong
Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
Graph matching-based algorithms for FPGA segmentation design. ICCAD (1998)
Youxin Gao, D. F. Wong
Shaping a VLSI wire to minimize delay using transmission line model. ICCAD (1998)
Wai-Kei Mak, D. F. Wong
Performance-driven board-level routing for FPGA-based logic emulation. ICCD (1998)
Hai Zhou, D. F. Wong
Global Routing with Crosstalk Constraints. DAC (1998)
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 1998 (1) (1998)
Fung Yu Young, D. F. Wong
How good are slicing floorplans?. ISPD (1997)
Huiqun Liu, D. F. Wong
Network flow based multi-way partitioning with area and pin constraints. ISPD (1997)
Chris C. N. Chu, D. F. Wong
A new approach to simultaneous buffer insertion and wire sizing. ICCAD (1997)
Wai-Kei Mak, D. F. Wong
Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2 (2) (1997)
Chris C. N. Chu, D. F. Wong
A matrix synthesis approach to thermal placement. ISPD (1997)
F. Y. Young, D. F. Wong
How good are slicing floorplans? Integr. 23 (1) (1997)
Chung-Ping Chen, D. F. Wong
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC (1997)
Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD (1997)
Yao-Ping Chen, D. F. Wong
On retiming for FPGA logic module minimization. Integr. 24 (2) (1997)
Hai Zhou, D. F. Wong
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD (1997)
Chris C. N. Chu, D. F. Wong
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD (1997)
Wai-Kei Mak, D. F. Wong
Channel Segmentation Design for Symmentrical FPGAs. ICCD (1997)
Youxin Gao, D. F. Wong
Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD (1997)
John F. Croix, D. F. Wong
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC (1997)
Yao-Ping Chen, D. F. Wong
A graph theoretic approach to feed-through pin assignment. Integr. 24 (2) (1997)
Fung Yu Young, D. F. Wong
On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD (1997)
Hai Zhou, D. F. Wong
An exact gate decomposition algorithm for low-power technology mapping. ICCAD (1997)
Yao-Wen Chang, D. F. Wong, C. K. Wong
Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1 (1) (1996)
Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC (1996)
Shashidhar Thakur, D. F. Wong
Universal Logic Modules for Series-Parallel Functions. FPGA (1996)
Yung-Ming Fang, D. F. Wong
Multiplexor Network Generation in High Level Synthesis. ICCD (1996)
Y. P. Chen, D. F. Wong
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. ED&TC (1996)
Chung-Ping Chen, Yao-Ping Chen, D. F. Wong
Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC (1996)
Shashidhar Thakur, D. F. Wong
Series-parallel functions and FPGA logic module design. ACM Trans. Design Autom. Electr. Syst. 1 (1) (1996)
Hai Zhou, D. F. Wong
An optimal algorithm for river routing with crosstalk constraints. ICCAD (1996)
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy
Delay Minimal Decomposition of Multiplexers in Technology Mapping. DAC (1996)
Wai-Kei Mak, D. F. Wong
Minimum replication min-cut partitioning. ICCAD (1996)
Yao-Wen Chang, D. F. Wong, C. K. Wong
Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA (1996)

D. F. Wong.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

D. F. Wong