Chris C. N. Chu

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 12

Top Topics

Asynchronous Circuits

Relaxation Algorithm

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. DAC (2016)
Gang Wu, Chris C. N. Chu
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits. DATE (2016)
Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel
Area optimization of resilient designs guided by a mixed integer geometric program. DAC (2016)
Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu
Flip-flop clustering by weighted K-means algorithm. DAC (2016)
Yixiao Ding, Chris C. N. Chu, Xin Zhou
An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT. DAC (2015)
Tao Lin, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Chris C. N. Chu, Wai-Kei Mak
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Gang Wu, Ankur Sharma, Chris C. N. Chu
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation. ASYNC (2015)
Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. DAC (2015)
Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD (2015)
Tao Lin, Chris C. N. Chu, Gang Wu
POLAR 3.0: An Ultrafast Global Placement Engine. ICCAD (2015)
Tao Lin, Chris C. N. Chu
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints. ISPD (2015)
Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (7) (2011)
Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
Handling routability in floorplan design with twin binary trees. Integr. 42 (4) (2009)
Chris C. N. Chu, Yiu-Chung Wong
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC (2007)
Min Pan, Chris C. N. Chu
IPR: An Integrated Placement and Routing Algorithm. DAC (2007)
Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia
The coming of age of physical synthesis. ICCAD (2007)
Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu
Wire Retiming Problem With Net Topology Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Min Pan, Chris C. N. Chu, Priyadarshan Patra
A Novel Performance-Driven Topology Design Algorithm. ASP-DAC (2007)
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. ASP-DAC (2007)
Min Pan, Chris C. N. Chu
FastRoute 2.0: A High-quality and Efficient Global Router. ASP-DAC (2007)
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu
Post-placement voltage island generation. ICCAD (2006)
Chuan Lin, Hai Zhou, Chris C. N. Chu
A revisit to floorplan optimization by Lagrangian relaxation. ICCAD (2006)
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu
Analog placement with symmetry and other placement constraints. ICCAD (2006)
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ASP-DAC (2006)
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
Optimal cell flipping in placement and floorplanning. DAC (2006)
Min Pan, Chris C. N. Chu
FastRoute: a step to integrate global routing into placement. ICCAD (2006)
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
FastPlace: an analytical placer for mixed-mode designs. ISPD (2005)
Chris C. N. Chu, Yiu-Chung Wong
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. ISPD (2005)
Min Pan, Chris C. N. Chu, J. Morris Chang
Transition time bounded low-power clock tree construction. ISCAS (3) (2005)
Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. ICCD (2005)
Min Pan, Chris C. N. Chu, Hai Zhou
Timing yield estimation using statistical static timing analysis. ISCAS (3) (2005)
Natarajan Viswanathan, Chris C. N. Chu
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Min Pan, Natarajan Viswanathan, Chris C. N. Chu
An efficient and effective detailed placement algorithm. ICCAD (2005)
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Debjit Sinha, Hai Zhou, Chris C. N. Chu
Optimal gate sizing for coupling-noise reduction. ISPD (2004)
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
Placement constraints in floorplan design. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Zion Cien Shen, Chris C. N. Chu
Accurate and efficient flow based congestion estimation in floorplanning. ASP-DAC (2004)
Chris C. N. Chu, Evangeline F. Y. Young
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ASP-DAC (2004)
Natarajan Viswanathan, Chris C. N. Chu
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ISPD (2004)
Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
Optimizing SOC Test Resources Using Dual Sequences. VLSI-SoC (Selected Papers) (2003)
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu
Retiming with Interconnect and Gate Delay. ICCAD (2003)
Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE (2003)
Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Zion Cien Shen, Chris C. N. Chu
Bounds on the number of slicing, mosaic, and general floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (10) (2003)
Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters
Dependable Handling of Uncertainty. Reliab. Comput. 9 (6) (2003)
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD (2002)
Chris C. N. Chu, Evangeline F. Y. Young
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE (2002)
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. VLSI Design (2002)
Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD (2002)
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ICCD (2002)
Yu-Yen Mo, Chris C. N. Chu
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (5) (2001)
Chris C. N. Chu, D. F. Wong
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6 (3) (2001)
Chris C. N. Chu, D. F. Wong
VLSI Circuit Performance Optimization by Geometric Programming. Ann. Oper. Res. 105 (1-4) (2001)
Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (5) (2001)
Yu-Yen Mo, Chris C. N. Chu
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. ISPD (2000)
Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
Floorplan area minimization using Lagrangian relaxation. ISPD (2000)
Chris C. N. Chu, Martin D. F. Wong
Greedy wire-sizing is linear time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Chris C. N. Chu, Martin D. F. Wong
An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Chris C. N. Chu, Martin D. F. Wong
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (6) (1999)
Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (7) (1999)
Fung Yu Young, Chris C. N. Chu, D. F. Wong
Generation of Universal Series-Parallel Boolean Functions. J. ACM 46 (3) (1999)
Chris C. N. Chu, D. F. Wong
Greedy wire-sizing is linear time. ISPD (1998)
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD (1998)
Chris C. N. Chu, Martin D. F. Wong
A matrix synthesis approach to thermal placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (11) (1998)
Chris C. N. Chu, D. F. Wong
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE (1998)
Chris C. N. Chu, D. F. Wong
A new approach to simultaneous buffer insertion and wire sizing. ICCAD (1997)
Chris C. N. Chu, D. F. Wong
A matrix synthesis approach to thermal placement. ISPD (1997)
Chris C. N. Chu, D. F. Wong
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD (1997)