Paul Villarrubia

Publication Activity (10 Years)

Years Active: 1989-2007
Publications (10 Years): 0

Publications

Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC (2007)
Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC (2007)
Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
Diffusion-based placement migration. DAC (2005)
Paul Villarrubia
Physical design tools for hierarchy. ISPD (2005)
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
A semi-persistent clustering technique for VLSI circuit placement. ISPD (2005)
Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
The ISPD2005 placement contest and benchmark suite. ISPD (2005)
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
Benchmarking for large-scale placement and beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Haoxing Ren, David Zhigang Pan, Paul Villarrubia
True crosstalk aware incremental placement with noise map. ICCAD (2004)
Paul Villarrubia
Important placement considerations for modern VLSI chips. ISPD (2003)
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
Benchmarking for large-scale placement and beyond. ISPD (2003)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. ICCAD (2003)
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
Free space management for cut-based placement. ICCAD (2002)
Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
Buffered Steiner trees for difficult instances. ISPD (2001)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC (2001)
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
"Timing closure by design, " a high frequency microprocessor design methodology. DAC (2000)
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
Transformational Placement and Synthesis. DATE (2000)
Shervin Hojat, Paul Villarrubia
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. ICCD (1997)
Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel
IBM RISC chip design methodology. ICCD (1989)