Shrirang K. Karandikar

Publication Activity (10 Years)

Years Active: 2001-2012
Publications (10 Years): 0

Top Topics

Clustering Method

Top Venues

Publications

Varad R. Deshmukh, Nishchay S. Mhatre, Shrirang K. Karandikar
FIRA - a novel method for benchmarking the cache hierarchy. COMPUTE (2012)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC (2007)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
Techniques for Fast Physical Synthesis. Proc. IEEE 95 (3) (2007)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
The nuts and bolts of physical synthesis. SLIP (2007)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
Fast algorithms for slew constrained minimum cost buffering. DAC (2006)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Fast comparisons of circuit implementations. IEEE Trans. Very Large Scale Integr. Syst. 13 (12) (2005)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) (2005)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Logical effort based technology mapping. ICCAD (2004)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Fast Comparisons of Circuit Implementations. DATE (2004)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. Very Large Scale Integr. Syst. 11 (6) (2003)
Shrirang K. Karandikar, Sachin S. Sapatnekar
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC (2001)