Cliff C. N. Sze

Publication Activity (10 Years)

Years Active: 2002-2017
Publications (10 Years): 5

Top Topics

Physical Design

Top Venues

Publications

He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze
Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB (2017)
Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Tiago Reimann, Cliff C. N. Sze, Ricardo Reis
Challenges of cell selection algorithms in industrial high performance microprocessor designs. Integr. 52 (2016)
Tiago J. Reimann, Cliff C. N. Sze, Ricardo Reis
Cell Selection for High-Performance Designs in an Industrial Design Flow. ISPD (2016)
He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi
GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI (2016)
Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Tiago Reimann, Cliff C. N. Sze, Ricardo Reis
Gate sizing and threshold voltage assignment for high performance microprocessor designs. ASP-DAC (2015)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP (2014)
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC (2013)
Thomas H. Osiecki, Min-Yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze
Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. ICCS (2013)
Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
Clock power minimization using structured latch templates and decision tree induction. ICCAD (2013)
Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
Routing congestion estimation with real design constraints. DAC (2013)
Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol
ISPD 2013 expert designer/user session (eds). ISPD (2013)
Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
CATALYST: planning layer directives for effective design closure. DATE (2013)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
The DAC 2012 routability-driven placement contest and benchmark suite. DAC (2012)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
GLARE: global and local wiring aware routability evaluation. DAC (2012)
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI (2012)
Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC (2012)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD (2012)
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55 (3) (2011)
David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31 (4) (2011)
Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
Grid-to-ports clock routing for high performance microprocessor designs. ISPD (2011)
Cliff C. N. Sze
The future of clock network synthesis. ICCAD (2011)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD (2011)
Cliff C. N. Sze
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD (2010)
Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD (2010)
Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz
The ISPD global routing benchmark suite. ISPD (2008)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
Techniques for Fast Physical Synthesis. Proc. IEEE 95 (3) (2007)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
The nuts and bolts of physical synthesis. SLIP (2007)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
Integrated placement and skew optimization for rotary clocking. DATE (2006)
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
Timing-driven Steiner trees are (practically) free. DAC (2006)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
Fast algorithms for slew constrained minimum cost buffering. DAC (2006)
Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Path based buffer insertion. DAC (2005)
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
Register placement for low power clock network. ASP-DAC (2005)
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
Navigating registers in placement for clock network minimization. DAC (2005)
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Making fast buffer insertion even faster via approximation techniques. ASP-DAC (2005)
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC (2005)
Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
A place and route aware buffered Steiner tree construction. ASP-DAC (2004)
Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (7) (2004)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
Accurate estimation of global buffer delay within a floorplan. ICCAD (2004)
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Cliff C. N. Sze, Ting-Chi Wang
Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Cliff C. N. Sze, Ting-Chi Wang
Multi-Level Circuit Clustering for Delay Minimization. IWLS (2002)
Cliff C. N. Sze, Ting-Chi Wang
Optimal circuit clustering with variable interconnect delay. ISCAS (4) (2002)