Yici Cai

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 49

Top Venues

ASP-DAC

ISCAS

Integr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Jianwang Zhai, Yici Cai, Bei Yu
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC (2023)
Haoyi Wang, Qiang Zhou, Yici Cai
Static Probability Analysis Guided RTL Hardware Trojan Test Generation. ASP-DAC (2023)
Jianwang Zhai, Yici Cai
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Lin Li, Yici Cai, Qiang Zhou
A survey on machine learning-based routing for VLSI physical design. Integr. 86 (2022)
Wenyan Wu, Yici Cai, Qiang Zhou
TransMarker: A Pure Vision Transformer for Facial Landmark Detection. ICPR (2022)
Rui Hao, Yici Cai, Qiang Zhou
Intelligent and kernelized placement: A survey. Integr. 86 (2022)
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD (2021)
Haoyi Wang, Yici Cai, Qiang Zhou
A game theory approach for RTL security verification resources allocation. CCF Trans. High Perform. Comput. 3 (1) (2021)
Jing Wang, Yici Cai, Qiang Zhou
A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. ISCAS (2021)
Wenyan Wu, Yici Cai, Qiang Zhou
SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data. FG (2021)
Jianwang Zhai, Yici Cai, Qiang Zhou
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Jing Wang, Yici Cai, Qiang Zhou
Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks. J. Comput. Sci. Technol. 36 (5) (2021)
Lin Li, Yici Cai, Qiang Zhou
An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. ISCAS (2021)
Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Wenyan Wu, Xingzhe Wu, Yici Cai, Qiang Zhou
Deep coupling neural network for robust facial landmark detection. Comput. Graph. 82 (2019)
Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou
A high-level information flow tracking method for detecting information leakage. Integr. 69 (2019)
Jing Wang, Yici Cai, Ming Yan, Qiang Zhou
Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. ISCAS (2019)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integr. 67 (2019)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (10) (2019)
Chenguang Wang, Yici Cai, Qiang Zhou
HLIFT: A high-level information flow tracking method for detecting hardware Trojans. ASP-DAC (2018)
Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou
Electromigration Design Rule aware Global and Detailed Routing Algorithm. ACM Great Lakes Symposium on VLSI (2018)
Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CVPR (2018)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
Spear and Shield: Evolution of Integrated Circuit Camouflaging. J. Comput. Sci. Technol. 33 (1) (2018)
Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1) (2018)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. ASP-DAC (2018)
Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CoRR (2018)
Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou
Electromagnetic equalizer: an active countermeasure against EM side-channel attack. ICCAD (2018)
Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang
ASAX: Automatic security assertion extraction for detecting Hardware Trojans. ASP-DAC (2018)
Jia Wei, Qiang Zhou, Yici Cai
Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks. ICNC (2018)
Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11 (6) (2017)
Xiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang
Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks. DATE (2017)
Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC (2017)
Chenguang Wang, Yici Cai, Qiang Zhou
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. ICCD (2017)
Yunxing Xin, Yongqiang Chen, Li Jin, Yici Cai, Ling Feng
TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy. BigData Congress (2017)
Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD (2017)
Xueyan Wang, Yici Cai, Qiang Zhou
Cell spreading optimization for force-directed global placers. ISCAS (2017)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. ACM Great Lakes Symposium on VLSI (2017)
Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou
An Effective Power Grid Optimization Approach for the Electromigration Reliability. ISVLSI (2017)
Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI (2017)
Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
Is the Secure IC camouflaging really secure? ISCAS (2016)
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI (2016)
Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD (2016)
Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu
An efficient framework for configurable RO PUF. ISCAS (2016)
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. ACM Great Lakes Symposium on VLSI (2016)
Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai
Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC (2016)
Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai
Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC (2015)
Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho
Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test 32 (6) (2015)
Chao Deng, Yici Cai, Qiang Zhou
Register Clustering Methodology for Low Power Clock Tree Synthesis. J. Comput. Sci. Technol. 30 (2) (2015)
Chao Deng, Yici Cai, Qiang Zhou
Fast synthesis of low power clock trees based on register clustering. ISQED (2015)
Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham
SIAR: Customized real-time interactive router for analog circuits. Integr. 48 (2015)
Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD (2015)
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Hailong Yao, Tsung-Yi Ho, Yici Cai
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC (2015)
Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Zhongdong Qi, Yici Cai, Qiang Zhou
Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths. J. Comput. Sci. Technol. 30 (3) (2015)
Wei Zhao, Yici Cai, Jianlei Yang
Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC (2014)
Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou
Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT (2014)
Chao Deng, Yici Cai, Qiang Zhou
A register clustering algorithm for low power clock tree synthesis. ISCAS (2014)
Yong-Qiang Lv, Qiang Zhou, Yici Cai, Gang Qu
Trusted Integrated Circuits: The Problem and Challenges. J. Comput. Sci. Technol. 29 (5) (2014)
Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang
Fast and scalable parallel layout decomposition in double patterning lithography. Integr. 47 (2) (2014)
Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang
Time-domain performance bound analysis for analog and interconnect circuits considering process variations. ASP-DAC (2014)
Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li
MCFRoute: a detailed router based on multi-commodity flow method. ICCAD (2014)
Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham
Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. 45 (6) (2014)
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen
VFGR: A very fast parallel global router with accurate congestion modeling. ASP-DAC (2014)
Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC (2014)
Zhongdong Qi, Yici Cai, Qiang Zhou
Accurate prediction of detailed routing congestion using supervised data learning. ICCD (2014)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Ziyang Qi, Kun Ma, Qiang Zhou, Yici Cai
RSMT construction algorithm based on Congestion-Oriented Flexibility. LASCAS (2014)
Wei Zhao, Yici Cai, Jianlei Yang
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC (2013)
Zhongdong Qi, Yici Cai, Qiang Zhou
Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model. CAD/Graphics (2013)
Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai
Performance bound and yield analysis for analog circuits under process variations. ASP-DAC (2013)
Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu
Design and Implementation of a Delay-Based PUF for FPGA IP Protection. CAD/Graphics (2013)
Zihao Chen, Hailong Yao, Yici Cai
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED (2013)
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
Selected inversion for vectorless power grid verification by exploiting locality. ICCD (2013)
Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. 46 (1) (2013)
Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou
A new splitting graph construction algorithm for SIAR router. ASICON (2013)
Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou
Analog routing considering min-area constraint. ASICON (2013)
Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai
A DyadicCluster method used for nonlinear placement. ISQED (2012)
Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie
Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC (2012)
Hailong Yao, Yici Cai, Qiang Gao
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC (2012)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush : Efficient transient simulation for power grid analysis. ICCAD (2012)
Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao
A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED (2011)
Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED (2011)
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
Fast poisson solver preconditioned method for robust power grid analysis. ICCAD (2011)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush: A linear simulator for power grid. ICCAD (2011)
Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai
SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI (2011)
Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai
A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD (2011)
Qiang Zhou, Jin Shi, Bin Liu, Yici Cai
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI (2011)
Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai
Statistical full-chip dynamic power estimation considering spatial correlations. ISQED (2011)
Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI (2011)
Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. Integr. 43 (1) (2010)
Jin Shi, Yici Cai
Scaling power/ground solvers on multi-core with memory bandwidth awareness. ACM Great Lakes Symposium on VLSI (2010)
Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu
Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED (2010)
Qiang Gao, Yin Shen, Yici Cai, Hailong Yao
Analog circuit shielding routing algorithm based on net classification. ISLPED (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Yici Cai