SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.

Qin Wang Weiran He Hailong Yao Tsung-Yi Ho Yici Cai

Published in: ISPD (2015)

Keyphrases

chip design
high speed
circuit design
feature selection
low cost
design process
single chip
case study
modular design
physical design
design methodology
higher level
power consumption
evolvable hardware
low power consumption
user interface
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