Hailong Yao

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 51

Top Topics

Design Methodology

Authentication Protocol

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ACM Great Lakes Symposium on VLSI

Publications

Caihui Lan, Haifeng Li, Caifen Wang, Xiaodong Yang, Hailong Yao
KASE-AKA: Key-aggregate keyword searchable encryption against keyword guessing attack and authorization abuse. Comput. Stand. Interfaces 90 (2024)
Weiqing Ji, Xingzhuo Guo, Shouan Pan, Fei Long, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. IEEE Trans. Biomed. Circuits Syst. 18 (3) (2024)
Chen Jiang, Rongquan Yang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan
A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. ACM Great Lakes Symposium on VLSI (2023)
Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. ICCAD (2023)
Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. ACM Great Lakes Symposium on VLSI (2023)
Jun Zeng, Panfeng Wang, Haili Wang, Hailong Yao, Fuchun Sun
A Compilation Toolchain of Neural Networks for FPGA Backend. ASICON (2023)
Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao
Contamination-Aware Synthesis for Programmable Microfluidic Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Hailong Yao, Qiao Yan, Xingbing Fu, Zhibin Zhang, Caihui Lan
ECC-based lightweight authentication and access control scheme for IoT E-healthcare. Soft Comput. 26 (9) (2022)
Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao
GEML: GNN-based efficient mapping method for large loop applications on CGRA. DAC (2022)
Jun Zeng, Mingyang Kou, Hailong Yao
NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis. NeurIPS (2022)
Jun Zeng, Mingyang Kou, Hailong Yao
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. ACM Great Lakes Symposium on VLSI (2022)
Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
GNN-based concentration prediction for random microfluidic mixers. DAC (2022)
Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho, Hailong Yao
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. ACM Great Lakes Symposium on VLSI (2021)
Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Zhiyang Chen, Weiqing Ji, Yihao Peng, Datao Chen, Mingyu Liu, Hailong Yao
Machine Learning Based Acceleration Method for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI (2021)
Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Bin Wu, Caifen Wang, Hailong Yao
A certificateless linearly homomorphic signature scheme for network coding and its application in the IoT. Peer-to-Peer Netw. Appl. 14 (2) (2021)
Lingxuan Shao, Wentai Li, Tsung-Yi Ho, Sudip Roy, Hailong Yao
Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Caifen Wang, Bin Wu, Hailong Yao
Leveled Adaptively Strong-Unforgeable Identity-Based Fully Homomorphic Signatures. IEEE Access 8 (2020)
Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Hailong Yao, Caifen Wang, Xingbing Fu, Chao Liu, Bin Wu, Fagen Li
Impersonation Attacks on Lightweight Anonymous Authenticated Key Exchange Scheme for IoT. IACR Cryptol. ePrint Arch. 2020 (2020)
Weiqing Ji, Tsung-Yi Ho, Hailong Yao
Transfer Learning-Based Microfluidic Design System for Concentration Generation∗. DAC (2020)
Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC (2020)
Jiayi Weng, Tsung-Yi Ho, Weiqing Ji, Peng Liu, Mengdi Bao, Hailong Yao
URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Weiqing Ji, Tsung-Yi Ho, Junchao Wang, Hailong Yao
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Yanyuet Man, Hailong Yao
Automatic Breast Cancer Grading of Histological Images using Dilated Residual Network. ICBBT (2019)
Qinghang Zhao, Wenyu Sun, Jiaqing Zhao, Jian Zhao, Hailong Yao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Hailong Yao, Xingbing Fu, Caifen Wang, Congcong Meng, Bo Hai, Shiqiang Zhu
Cryptanalysis and Improvement of a Remote Anonymous Authentication Protocol for Mobile Multi-server Environments. DSC (2019)
Hailong Yao, Caifen Wang, Xingbing Fu, Chao Liu, Bin Wu, Fagen Li
A Privacy-Preserving RLWE-Based Remote Biometric Authentication Scheme for Single and Multi-Server Environments. IEEE Access 7 (2019)
Hailong Yao, Caifen Wang
A Novel Blockchain-Based Authenticated Key Exchange Protocol and Its Applications. DSC (2018)
Bo Hai, Hailong Yao
An Approach to Information Fusion and Group Deecision Making Based on Choquet Integral Operators for Interval-Valued Intuitionistic Fuzzy Data. ICMLC (2018)
Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Weiqing Ji, Tsung-Yi Ho, Hailong Yao
More Effective Randomly-Designed Microfluidics. ISVLSI (2018)
Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho
A Comprehensive Security System for Digital Microfluidic Biochips. ITC-Asia (2018)
Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD (2018)
Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits. ACM Trans. Design Autom. Electr. Syst. 23 (2) (2018)
Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11 (6) (2017)
Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC (2017)
Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC (2017)
Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR (2017)
Andreas Grimmer, Qin Wang, Hailong Yao, Tsung-Yi Ho, Robert Wille
Close-to-optimal placement and routing for continuous-flow microfluidic biochips. ASP-DAC (2017)
Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. DAC (2017)
Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI (2017)
Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD (2016)
Hongmei Zhao, Hailong Yao, Shuting Guo
Research on path loss and shadow fading of ultra wideband simulation channel. Int. J. Distributed Sens. Networks 12 (12) (2016)
Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai
Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC (2016)
Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho
Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test 32 (6) (2015)
Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham
SIAR: Customized real-time interactive router for analog circuits. Integr. 48 (2015)
Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD (2015)
Hailong Yao, Tsung-Yi Ho, Yici Cai
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC (2015)
Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
Slicing Floorplans with Handling Symmetry and General Placement Constraints. ISVLSI (2014)
Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang
Fast and scalable parallel layout decomposition in double patterning lithography. Integr. 47 (2) (2014)
Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham
Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. 45 (6) (2014)
Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC (2014)
Zihao Chen, Hailong Yao, Yici Cai
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED (2013)
Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou
A new splitting graph construction algorithm for SIAR router. ASICON (2013)
Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou
Analog routing considering min-area constraint. ASICON (2013)
Hailong Yao, Yici Cai, Qiang Gao
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC (2012)
Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao
A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED (2011)
Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED (2011)
Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai
SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI (2011)
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI (2011)
Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI (2011)
Qiang Gao, Yin Shen, Yici Cai, Hailong Yao
Analog circuit shielding routing algorithm based on net classification. ISLPED (2010)
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (6) (2010)
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED (2009)
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
Layout decomposition for double patterning lithography. ICCAD (2008)
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC (2008)
Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2 (1) (2008)
Hailong Yao, Yici Cai, Xianlong Hong
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI (2007)
Xianlong Hong, Yici Cai, Hailong Yao, Duo Li
DFM-aware Routing for Yield Enhancement. APCCAS (2006)
Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs (10) (2006)
Hailong Yao, Yici Cai, Xianlong Hong
Congestion-driven W-shape multilevel full-chip routing framework. ISCAS (2006)
Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai
Efficient process-hotspot detection using range pattern matching. ICCAD (2006)
Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20 (2) (2005)
Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI (2005)
Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
Crosstalk driven routing resource assignment. ISCAS (5) (2004)