Chin Ngai Sze

Publication Activity (10 Years)

Years Active: 2000-2014
Publications (10 Years): 0

Top Venues

ICCAD

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Texas A&M University, College Station, USA (PHD)

Education History

Texas A&M University, College Station, USA

PHD

Publications

Cheng-Kok Koh, Chin Ngai Sze
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward
Placement: Hot or Not? ICCAD (2012)
Michael D. Moffitt, Chin Ngai Sze
Wire synthesizable global routing for timing closure. ASP-DAC (2011)
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI (2011)
Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE (2010)
Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD (2008)
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD (2008)
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Chin Ngai Sze, Ting-Chi Wang
Performance-driven multi-level clustering for combinational circuits. ASP-DAC (2003)
Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian
Accelerating Logic Rewiring Using Implication Analysis Tree. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Chin Ngai Sze, Yu-Liang Wu
Improved alternative wiring scheme applying dominator relationship. ASP-DAC (2001)
Yu-Liang Wu, Chin Ngai Sze, Chak-Chung Cheung, Hongbing Fan
On improved graph-based alternative wiring scheme for multi-level logic optimization. ICECS (2000)

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Publication Activity (10 Years)

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Chin Ngai Sze