Michael Orshansky

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 32

Top Topics

Power Management

Countermeasures

Provably Secure

Top Venues

Publications

Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Andreas Gerstlauer, Ali E. Yilmaz
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements. ACM Trans. Embed. Comput. Syst. 23 (1) (2024)
Xiaodan Xi, Ge Li, Ye Wang, Michael Orshansky
A Provably Secure Strong PUF Based on LWE: Construction and Implementation. IEEE Trans. Computers 72 (2) (2023)
Zihao Deng, Benjamin Ghaemmaghami, Ashish Kumar Singh, Benjamin Y. Cho, Leo Orshansky, Mattan Erez, Michael Orshansky
Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training. CoRR (2023)
Xiaodan Xi, Ge Li, Ye Wang, Yeonsoo Jeon, Michael Orshansky
A Provably Secure Strong PUF based on LWE: Construction and Implementation. CoRR (2023)
Yeonsoo Jeon, Mattan Erez, Michael Orshansky
Artemis: HE-Aware Training for Efficient Privacy-Preserving Machine Learning. CoRR (2023)
Zihao Deng, Xin Wang, Sayeh Sharify, Michael Orshansky
Mixed-Precision Quantization with Cross-Layer Dependencies. CoRR (2023)
Ge Li, Mohit Tiwari, Michael Orshansky
Power-based Attacks on Spatial DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18 (3) (2022)
Zihao Deng, Michael Orshansky
Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. DATE (2022)
Aditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, Michael Orshansky
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks. SAMOS (2022)
Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC (2021)
Zihao Deng, Michael Orshansky
Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. CoRR (2021)
Furkan Aydin, Aydin Aysu, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols. ACM Trans. Embed. Comput. Syst. 20 (6) (2021)
Ge Li, Mohit Tiwari, Michael Orshansky
Power-Based Attacks on Spatial DNN Accelerators. CoRR (2021)
Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. CICC (2021)
Ye Wang, Xiaodan Xi, Michael Orshansky
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. HOST (2020)
Haoyu Zhuang, Xiaodan Xi, Nan Sun, Michael Orshansky
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Benjamin Ghaemmaghami, Zihao Deng, Benjamin Y. Cho, Leo Orshansky, Ashish Kumar Singh, Mattan Erez, Michael Orshansky
Training with Multi-Layer Embeddings for Model Reduction. CoRR (2020)
Ye Wang, Xiaodan Xi, Michael Orshansky
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. CoRR (2019)
Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, Mohit Tiwari
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. HOST (2019)
Ge Li, Vishnuvardhan V. Iyer, Michael Orshansky
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow. HOST (2019)
Ye Wang, Michael Orshansky
Efficient helper data reduction in SRAM PUFs via lossy compression. DATE (2018)
Aydin Aysu, Michael Orshansky, Mohit Tiwari
Binary Ring-LWE hardware with power side-channel countermeasures. DATE (2018)
Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols. HOST (2018)
Xiaodan Xi, Aydin Aysu, Michael Orshansky
Fresh re-keying with strong PUFs: A new approach to side-channel security. HOST (2018)
Amit Kumar, Cody Scarborough, Ali E. Yilmaz, Michael Orshansky
Efficient simulation of EM side-channel attack resilience. ICCAD (2017)
Aydin Aysu, Ye Wang, Patrick Schaumont, Michael Orshansky
A new maskless debiasing method for lightweight physical unclonable functions. HOST (2017)
Ye Wang, Constantine Caramanis, Michael Orshansky
PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation. DATE (2016)
Ye Wang, Constantine Caramanis, Michael Orshansky
Exploiting randomness in sketching for efficient hardware implementation of machine learning applications. ICCAD (2016)
Jaeyoung Park, Michael Orshansky
Multiple Attempt Write Strategy for Low Energy STT-RAM. ACM Great Lakes Symposium on VLSI (2016)
Jaeyoung Park, Tianhao Zheng, Mattan Erez, Michael Orshansky
Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Meng Li, Ye Wang, Michael Orshansky
A Monte Carlo simulation flow for SEU analysis of sequential circuits. DAC (2016)
Ye Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky, Constantine Caramanis
Novel power grid reduction method based on L1 regularization. DAC (2015)
Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky
Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Jin Miao, Andreas Gerstlauer, Michael Orshansky
Multi-level approximate logic synthesis under general error constraints. ICCAD (2014)
Ye Wang, Michael Orshansky, Constantine Caramanis
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization. DAC (2014)
Tianhao Zheng, Jaeyoung Park, Michael Orshansky, Mattan Erez
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring. ISLPED (2013)
Jie Han, Michael Orshansky
Approximate computing: An emerging paradigm for energy-efficient design. ETS (2013)
Ku He, Andreas Gerstlauer, Michael Orshansky
Low-energy digital filter design based on controlled timing error acceptance. ISQED (2013)
Jin Miao, Andreas Gerstlauer, Michael Orshansky
Approximate logic synthesis under general error magnitude and frequency constraints. ICCAD (2013)
Ku He, Andreas Gerstlauer, Michael Orshansky
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems. IEEE Trans. Circuits Syst. Video Technol. 23 (6) (2013)
Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun
Probabilistic strain optimization under constraint uncertainty. BMC Syst. Biol. 7 (2013)
Mukund Kalyanaraman, Michael Orshansky
Novel strong PUF based on nonlinearity of MOSFET subthreshold operation. HOST (2013)
Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun
Gene modification identification under flux capacity uncertainty. DAC (2013)
Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis, Michael Orshansky
Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (10) (2012)
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan
An accurate sparse-matrix based framework for statistical static timing analysis. Integr. 45 (4) (2012)
Ku He, Andreas Gerstlauer, Michael Orshansky
Low-energy signal processing using circuit-level timing-error acceptance. ICICDT (2012)
Mukund Kalyanaraman, Michael Orshansky
Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation. IACR Cryptol. ePrint Arch. 2012 (2012)
Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky
Modeling and synthesis of quality-energy optimal approximate adders. ICCAD (2012)
Kareem Ragab, Ranjit Gharpurey, Michael Orshansky
Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation. ISQED (2012)
Ku He, Andreas Gerstlauer, Michael Orshansky
Controlled timing-error acceptance for low energy IDCT design. DATE (2011)
Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky
Coupling timing objectives with optical proximity correction for improved timing yield. ISQED (2011)
Mehmet Basoglu, Michael Orshansky, Mattan Erez
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. ISLPED (2010)
Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky
An algorithm for exploiting modeling error statistics to enable robust analog optimization. ICCAD (2010)
Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky
SMATO: Simultaneous mask and target optimization for improving lithographic process window. ICCAD (2010)
Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky
Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. CICC (2010)
Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE (2010)
Michael Orshansky, Wei-Shen Wang
Statistical analysis of circuit timing using majorization. Commun. ACM 52 (8) (2009)
Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky
Mitigation of intra-array SRAM variability using adaptive voltage architecture. ICCAD (2009)
Bin Zhang, Michael Orshansky
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ISQED (2008)
Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey
The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. 25 (4) (2008)
Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky
Electrically driven optical proximity correction based on linear programming. ICCAD (2008)
Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham
Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI (2007)
Wei-Shen Wang, Michael Orshansky
Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electron. 3 (1) (2007)
Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. 4 (1) (2007)
Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC (2007)
Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. NANOARCH (2007)
Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies CoRR (2007)
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC (2006)
Wei-Shen Wang, Michael Orshansky
Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD (2006)
Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang
Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC (2006)
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC (2006)
Wei-Shen Wang, Michael Orshansky
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
Analytical modeling of SRAM dynamic stability. ICCAD (2006)
Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
Tutorial II: Variability and Its Impact on Design. ISQED (2006)
Bin Zhang, Wei-Shen Wang, Michael Orshansky
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED (2006)
Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky
BulletProof: a defect-tolerant CMP switch architecture. HPCA (2006)
Murari Mani, Ashish Kumar Singh, Michael Orshansky
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD (2006)
Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
An accurate sparse matrix based framework for statistical static timing analysis. ICCAD (2006)
Murari Mani, Mahesh Sharma, Michael Orshansky
Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI (2006)
Joonsoo Kim, Michael Orshansky
Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI (2006)
Wei-Shen Wang, Michael Liu, Michael Orshansky
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electron. 2 (1) (2006)
Ashish Kumar Singh, Murari Mani, Michael Orshansky
Statistical technology mapping for parametric yield. ICCAD (2005)
Murari Mani, Anirudh Devgan, Michael Orshansky
An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC (2005)
Murari Mani, Michael Orshansky
A New Statistical Optimization Algorithm for Gate Sizing. ICCD (2004)
Michael Liu, Wei-Shen Wang, Michael Orshansky
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED (2004)
Michael Orshansky, Arnab Bandyopadhyay
Fast statistical timing analysis handling arbitrary delay correlations. DAC (2004)
David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED (2003)
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (5) (2002)
Michael Orshansky, Kurt Keutzer
A general probabilistic framework for worst case timing analysis. DAC (2002)
Kurt Keutzer, Michael Orshansky
From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu
Efficient generation of pre-silicon MOS model parameters for early circuit design. IEEE J. Solid State Circuits 36 (1) (2001)
Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC (2000)
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD (2000)
Michael Orshansky, James C. Chen, Chenming Hu
A Statistical Performance Simulation Methodology for VLSI Circuits. DAC (1998)