Sanu K. Mathew

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 18

Top Topics

Encryption Decryption

Physical Design

Top Venues

IEEE J. Solid State Circuits

ACM Great Lakes Symposium on VLSI

Publications

Mao Li, Zhaoqing Wang, Sanu K. Mathew, Vivek De, Mingoo Seok
16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS. ISSCC (2024)
Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits 59 (1) (2024)
Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits. ISSCC (2024)
Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits 58 (4) (2023)
Masum Hossain, Arijit Raychowdhury, Sanu K. Mathew, Yakun Sophia Shao, Yih Wang
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 58 (1) (2023)
Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. ISSCC (2022)
Sanu K. Mathew
Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms. ACM Great Lakes Symposium on VLSI (2022)
Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE J. Solid State Circuits 56 (4) (2021)
Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC (2021)
Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew
839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55 (4) (2020)
Arvind Singh, Monodeep Kar, Venkata Chaitanya Krishna Chekuri, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. IEEE J. Solid State Circuits 55 (2) (2020)
Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC (2020)
Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Arvind Singh, Monodeep Kar, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. IEEE J. Solid State Circuits 54 (2) (2019)
Monodeep Kar, Arvind Singh, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator. IEEE J. Solid State Circuits 53 (8) (2018)
Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52 (4) (2017)
Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ISSCC (2016)
Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits 51 (7) (2016)
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50 (1) (2015)
Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, R. J. Parker, Ram K. Krishnamurthy, Vivek De
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC (2014)
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC (2014)
Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44 (1) (2009)
Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43 (1) (2008)
Sapumal B. Wijeratne, Nanda Siddaiah, Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Jeremy Anderson, Matthew Ernest, Mark D. Nardin
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. IEEE J. Solid State Circuits 42 (1) (2007)
Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits 41 (1) (2006)
Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. IEEE J. Solid State Circuits 40 (1) (2005)
Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends. IEEE J. Solid State Circuits 36 (11) (2001)