Shekhar Borkar

Publication Activity (10 Years)

Years Active: 1988-2021
Publications (10 Years): 2

Top Venues

ISSCC

IEEE J. Solid State Circuits

Commun. ACM

ASP-DAC

Publications

Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung-Kyu Lim, Ozgur Sinanoglu, Ramesh Karri
Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD (2021)
Vincent Cavé, Romain Cledat, Paul Griffin, Ankit More, Bala Seshasayee, Shekhar Borkar, Sanjay Chatterjee, Dave Dunning, Joshua B. Fryman
Traleika Glacier: A hardware-software co-designed approach to exascale computing. Parallel Comput. 64 (2017)
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50 (1) (2015)
Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Borkar, Patrick Yin Chiang
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. CICC (2014)
Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar
Resiliency for many-core system on a chip. ASP-DAC (2014)
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC (2014)
Shekhar Borkar
Centip3De demonstrates more than Moore...: technical perspective. Commun. ACM 56 (11) (2013)
Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA (2013)
Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore
EP3: Empowering the killer SoC applications of 2020. ISSCC (2013)
Tanay Karnik, Mondira (Mandy) Pant, Shekhar Borkar
Power management and delivery for high-performance microprocessors. DAC (2013)
Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits 48 (1) (2013)
Shekhar Borkar
Exascale Computing - A Fact or a Fiction? IPDPS (2013)
Masaitsu Nakajima, Shekhar Borkar
Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. ISSCC (2012)
Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC (2012)
Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC (2012)
Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC (2012)
Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
Near-threshold voltage (NTV) design: opportunities and challenges. DAC (2012)
Richard F. Barrett, Shekhar Borkar, Sudip S. Dosanjh, Simon D. Hammond, Michael A. Heroux, Xiaobo Sharon Hu, Justin Luitjens, Steven G. Parker, John Shalf, Li Tang
On the Role of Co-design in High Performance Computing. High Performance Computing Workshop (2) (2012)
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC (2012)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Shekhar Borkar, Andrew A. Chien
The future of microprocessors. Commun. ACM 54 (5) (2011)
Shekhar Borkar
3D integration for energy efficient system design. DAC (2011)
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
3DICs for tera-scale computing: a case study. ISPD (2011)
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. 5 (3) (2011)
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46 (1) (2011)
Donald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar
Integrated inductors with magnetic materials for on-chip power conversion. Hot Chips Symposium (2011)
Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC (2010)
Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC (2010)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC (2010)
Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits 45 (1) (2010)
Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra
The semiconductor industry in 2025. ISSCC (2010)
Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC (2010)
Shekhar Borkar
Design perspectives on 22nm CMOS and beyond. DAC (2009)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC (2009)
Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44 (1) (2009)
David Yeh, Li-Shiuan Peh, Shekhar Borkar, John A. Darringer, Anant Agarwal, Wen-mei W. Hwu
Thousand-Core Chips [Roundtable]. IEEE Des. Test Comput. 25 (3) (2008)
Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Hoskote, Nitin Borkar, Shekhar Borkar
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43 (1) (2008)
Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43 (1) (2008)
Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye
Custom is from Venus and synthesis from Mars. DAC (2008)
Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar
A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC (2008)
Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC (2008)
Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar
A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro 27 (5) (2007)
Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC (2007)
Shekhar Borkar, Norman P. Jouppi, Per Stenström
Microprocessors in the era of terascale integration. DATE (2007)
Shekhar Borkar, William J. Dally
Future of on-chip interconnection architectures. ISLPED (2007)
Shekhar Borkar
Thousand Core ChipsA Technology Perspective. DAC (2007)
Shekhar Borkar
Electronics beyond nano-scale CMOS. DAC (2006)
Shekhar Borkar
Probabilistic amp; Statistical Design - the Wave of the Future. VLSI-SoC (Selected Papers) (2006)
Shekhar Borkar
Introduction to panel discussion Probabilistic & statistical design - the wave of the future. VLSI-SoC (2006)
Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini
Tomorrow's analog: just dead or just different? DAC (2006)
Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC (2006)
Shekhar Borkar
Tackling variability and reliability challenges. IEEE Des. Test Comput. 23 (6) (2006)
Shekhar Borkar
VLSI Design Challenges for Gigascale Integration. VLSI Design (2005)
Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits 40 (4) (2005)
Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. IEEE J. Solid State Circuits 40 (1) (2005)
Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits 40 (4) (2005)
Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS (2005)
Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED (2005)
Shekhar Borkar
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro 25 (6) (2005)
Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. IEEE J. Solid State Circuits 40 (1) (2005)
Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. IEEE J. Solid State Circuits 39 (3) (2004)
Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar
A low-swing single-ended L1 cache bus technique for sub-90nm technologies. ESSCIRC (2004)
Shekhar Borkar, Tanay Karnik, Vivek De
Design and reliability challenges in nanometer technologies. DAC (2004)
Shekhar Borkar
Microarchitecture and Design Challenges for Gigascale Integration. MICRO (2004)
Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
CMOS process. IEEE J. Solid State Circuits 39 (9) (2004)
Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson
Bitline leakage equalization for sub-100nm caches. ESSCIRC (2003)
Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED (2003)
Shekhar Borkar
Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. ACM Queue 1 (7) (2003)
Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid State Circuits 38 (5) (2003)
Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
Parameter variations and impact on circuits and microarchitecture. DAC (2003)
Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar
Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC (2003)
Shekhar Borkar
Exponential Challenges, Exponential Rewards - The future of Moore's Law. VLSI-SOC (2003)
Shekhar Borkar, Yoshinobu Nakagome
Guest Editorial. IEEE J. Solid State Circuits 38 (5) (2003)
Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38 (5) (2003)
Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar
A transition-encoded dynamic bus technique for high-performance interconnects. IEEE J. Solid State Circuits 38 (5) (2003)
Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
Nanometer design: place your bets. DAC (2003)
Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC (2003)
James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De
Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits 38 (11) (2003)
Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De
Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid State Circuits 38 (5) (2003)
Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC (2002)
Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De
SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10 (2) (2002)
Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar
High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC (2002)
Tanay Karnik, Shekhar Borkar, Vivek De
Sub-90nm technologies: challenges and opportunities for CAD. ICCAD (2002)
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
CMOS. IEEE J. Solid State Circuits 37 (11) (2002)
Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb
A burn-in tolerant dynamic circuit technique. CICC (2002)
Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED (2002)
George Sery, Shekhar Borkar, Vivek De
Life is CMOS: why chase the life after? DAC (2002)
Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar
A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED (2001)
Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar
Scaling of stack effect and its application for leakage reduction. ISLPED (2001)
Shekhar Borkar
Low power design challenges for the decade (invited talk). ASP-DAC (2001)
James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED (2001)
Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI (2001)
Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED (2001)
Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
Panel: Is Nanometer Design Under Control? DAC (2001)
Vivek De, Shekhar Borkar
Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI (2000)
Vivek De, Shekhar Borkar
Technology and design challenges for low power and high performance. ISLPED (1999)
Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel
Accurate on-chip interconnect evaluation: a time-domain technique. IEEE J. Solid State Circuits 34 (5) (1999)
Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED (1999)

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Publication Activity (10 Years)

Top Topics

Top Venues

Shekhar Borkar