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A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme.
Steven Hsu
Atila Alvandpour
Sanu Mathew
Shih-Lien Lu
Ram K. Krishnamurthy
Shekhar Borkar
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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knowledge base
garbage collection
caching scheme
prefetching
data structure
cache replacement
image compression
operating system
data access
replacement policy
hit rate