Ram K. Krishnamurthy

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 17

Top Topics

Automatic Speech Recognition

Top Venues

IEEE J. Solid State Circuits

Publications

Zhaoqing Wang, Mao Li, Suhwan Kim, Nachiket V. Desai, Ram K. Krishnamurthy, Xin Zhang, Mingoo Seok
A Ten-Level Series-Capacitor 24-to-1-V DC-DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail. IEEE J. Solid State Circuits 59 (7) (2024)
Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. IEEE J. Solid State Circuits 58 (4) (2023)
Dewei Wang, Jonghyun Oh, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok
microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware. ESSCIRC (2023)
Zhaoqing Wang, Mao Li, Suhwan Kim, Nachiket V. Desai, Ram K. Krishnamurthy, Orlando Lazaro, Andres Blanco, Xin Zhang, Mingoo Seok
93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming. ESSCIRC (2023)
Zhiyuan Zhou, Nghia Tang, Bai Nguyen, Wookpyo Hong, Partha Pratim Pande, Ram K. Krishnamurthy, Deukhyoun Heo
An Inductor-First Single-Inductor Multiple-Output Hybrid DC-DC Converter With Integrated Flying Capacitor for SoC Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. VLSI Technology and Circuits (2022)
Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56 (4) (2021)
Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew
839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55 (4) (2020)
Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC (2020)
Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits (2020)
Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Ram K. Krishnamurthy
Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities. SoCC (2019)
Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits (2018)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. CICC (2017)
Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52 (4) (2017)
Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits 51 (7) (2016)
Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, R. J. Parker, Ram K. Krishnamurthy, Vivek De
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC (2014)
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC (2014)
Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits 48 (1) (2013)
Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 48 (1) (2013)
Donhee Ham, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 44 (1) (2009)
Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44 (1) (2009)
Shuvra S. Bhattacharyya, Jeffery C. Bier, Wanda K. Gass, Ram K. Krishnamurthy, Edward A. Lee, Konstantinos Konstantinides
Advances in hardware design and implementation of signal processing systems [DSP Forum]. IEEE Signal Process. Mag. 25 (6) (2008)
Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43 (1) (2008)
David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43 (1) (2008)
Amit Agarwal, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS. ESSCIRC (2007)
Sapumal B. Wijeratne, Nanda Siddaiah, Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Jeremy Anderson, Matthew Ernest, Mark D. Nardin
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. IEEE J. Solid State Circuits 42 (1) (2007)
Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits 41 (1) (2006)
Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. IEEE J. Solid State Circuits 40 (1) (2005)
Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar
A low-swing single-ended L1 cache bus technique for sub-90nm technologies. ESSCIRC (2004)
Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy
A leakage-tolerant low-leakage register file with conditional sleep transistor. SoCC (2004)
Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid State Circuits 38 (5) (2003)
Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38 (5) (2003)
Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar
A transition-encoded dynamic bus technique for high-performance interconnects. IEEE J. Solid State Circuits 38 (5) (2003)
Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar
A sub-130-nm conditional keeper technique. IEEE J. Solid State Circuits 37 (5) (2002)
Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits 37 (5) (2002)
Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar
High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC (2002)
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
CMOS. IEEE J. Solid State Circuits 37 (11) (2002)
Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends. IEEE J. Solid State Circuits 36 (11) (2001)
L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy
Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. ISLPED (1998)
Ram K. Krishnamurthy, L. Richard Carley
Exploring the design space of mixed swing quadrail for low-power digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5 (4) (1997)
Ram K. Krishnamurthy, Ihor Lys, L. Richard Carley
Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. ISLPED (1996)
Venu Govindaraju, Ram K. Krishnamurthy
Holistic handwritten word recognition using temporal features derived from off-line images. Pattern Recognit. Lett. 17 (5) (1996)
Ram K. Krishnamurthy, Ramalingam Sridhar
A CMOS wave-pipelined image processor for real-time morphology . ICCD (1995)