Dinesh Somasekhar

Publication Activity (10 Years)

Years Active: 1993-2016
Publications (10 Years): 4

Top Topics

Power Management

Digital Circuits

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE J. Solid State Circuits

Publications

Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Toshiaki Kirihata, Dinesh Somasekhar
Advanced memory topics. CICC (2014)
Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. IEEE J. Solid State Circuits 49 (11) (2014)
Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De
A fully-digital phase-locked low dropout regulator in 32nm CMOS. VLSIC (2012)
Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
3DICs for tera-scale computing: a case study. ISPD (2011)
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. 5 (3) (2011)
James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
Resilient design in scaled CMOS for energy efficiency. ASP-DAC (2010)
Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits 45 (4) (2010)
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA (2010)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44 (4) (2009)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC (2008)
James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC (2007)
Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42 (1) (2007)
Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
Fine-Grained Redundancy in Adders. ISQED (2007)
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS (2006)
Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
SRAM Building Block in 65nm CMOS. ISSCC (2006)
Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC (2005)
Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson
Bitline leakage equalization for sub-100nm caches. ESSCIRC (2003)
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De
technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38 (5) (2003)
Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
CMOS. IEEE J. Solid State Circuits 37 (11) (2002)
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD (2000)
Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
Dynamic noise analysis in precharge-evaluate circuits. DAC (2000)
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (6) (1999)
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC (1999)
Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD (1999)
Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI (1998)
Dinesh Somasekhar, Kaushik Roy
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Dinesh Somasekhar, Kaushik Roy
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED (1997)
Dinesh Somasekhar, Kaushik Roy
Differential current switch logic: a low power DCVS logic family. IEEE J. Solid State Circuits 31 (7) (1996)
Dinesh Somasekhar, V. Visvanathan
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Dinesh Somasekhar, V. Visvanathan
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design (1993)