Keith A. Bowman

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 21

Top Topics

Digital Circuits

Power Management

Top Venues

IEEE J. Solid State Circuits

Publications

Daniel Yingling, Yimai Peng, Robert Vachon, Dipti Pal, Sagar Jariwala, Felipe G. Cabral, Jason Hu, Rajan Verma, Vamshidhar Chiranji, Anil Kumar, Santanu Sarma, Keith A. Bowman
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion. ISSCC (2024)
Zhaoqing Wang, Sung Justin Kim, Keith A. Bowman, Mingoo Seok
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators. CICC (2022)
Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC (2021)
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Suresh Venkumahanti
35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor. ISSCC (2021)
Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. ISSCC (2021)
Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof
F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC (2021)
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. IEEE J. Solid State Circuits 56 (4) (2021)
Arijit Raychowdhury, Mijung Noh, Keith A. Bowman
Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. ISSCC (2021)
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. IEEE J. Solid State Circuits 56 (3) (2021)
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor. VLSI Circuits (2020)
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP. CICC (2020)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54 (4) (2019)
Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC (2019)
Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits (2019)
Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 53 (1) (2018)
Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. VLSI Circuits (2018)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits (2018)
Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC (2017)
Makoto Takamiya, Yogesh K. Ramadass, Keith A. Bowman, Gerard Villar Pique, Shuichi Nagai, Dennis Sylvester
F1: Integrated voltage regulators for SoC and emerging IoT systems. ISSCC (2017)
Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. 84 (3) (2016)
Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE J. Solid State Circuits 51 (1) (2016)
Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. CICC (2015)
Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. ISSCC (2015)
Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS (2014)
Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. CICC (2014)
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC (2014)
Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. ITC (2014)
Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi
Welcome to ISQED 2013. ISQED (2013)
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De
Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test 30 (6) (2013)
Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits 48 (4) (2013)
Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED (2013)
Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky
Design for test and reliability in ultimate CMOS. DATE (2012)
Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC (2012)
Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC (2012)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46 (1) (2011)
Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46 (4) (2011)
Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
Resilient design in scaled CMOS for energy efficiency. ASP-DAC (2010)
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
Resilient microprocessor design for high performance & energy efficiency. ISLPED (2010)
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC (2010)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC (2010)
Keith A. Bowman, James W. Tschanz
Resilient microprocessor design for improving performance and energy efficiency. ICCAD (2010)
James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC (2010)
Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC (2010)
Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 44 (1) (2009)
Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
Circuit techniques for dynamic variation tolerance. DAC (2009)
James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik
Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD (2009)
Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC (2008)
Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. ISLPED (2007)
Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
Comparative Analysis of Conventional and Statistical Design Techniques. DAC (2007)
Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26 (6) (2006)
Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
Tutorial II: Variability and Its Impact on Design. ISQED (2006)
Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED (2006)
James W. Tschanz, Keith A. Bowman, Vivek De
Variation-tolerant circuits: circuit solutions and techniques. DAC (2005)
Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD (2005)
Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED (2005)
Keith A. Bowman, Steven G. Duvall, James D. Meindl
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37 (2) (2002)
Keith A. Bowman, James D. Meindl
Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC (2001)
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP (2000)
Keith A. Bowman, Xinghai Tang, John C. Eble, James D. Menldl
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. IEEE J. Solid State Circuits 35 (8) (2000)
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED (2000)
Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8 (3) (2000)
Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl
A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits 34 (10) (1999)