Visvesh S. Sathe

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 21

Top Topics

Bias Correction

Integrated Circuit

Predictive Control

Top Venues

IEEE J. Solid State Circuits

Publications

Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 59 (1) (2024)
Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. IEEE J. Solid State Circuits 58 (1) (2023)
Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. ISSCC (2022)
Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57 (1) (2022)
Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. ISSCC (2022)
Arindam Mandal, Diego Peña, Rajesh Pamula, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. CICC (2021)
Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits (2020)
Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits 55 (2) (2020)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Jacques Christophe Rudell, Visvesh S. Sathe
/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression. IEEE Trans. Biomed. Circuits Syst. 14 (2) (2020)
Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits (2020)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54 (4) (2019)
Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe
-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54 (11) (2019)
Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC (2018)
Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh S. Sathe
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits (2018)
Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits (2018)
Vincent T. Lee, Armin Alaghi, Rajesh Pamula, Visvesh S. Sathe, Luis Ceze, Mark Oskin
Architecture Considerations for Stochastic Computing Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Fahim U. Rahman, Visvesh S. Sathe
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. ISSCC (2016)
Patrick Chiang, Visvesh S. Sathe
Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 51 (8) (2016)
Ta-Tung Yen, Bin Yu, Visvesh S. Sathe
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. DATE (2016)
William Anthony Smith, Brian Mogen, Eberhard E. Fetz, Visvesh S. Sathe, Brian P. Otis
Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements. IEEE Trans. Biomed. Circuits Syst. 10 (6) (2016)
Visvesh S. Sathe, Jae-sun Seo
Analysis and optimization of CMOS switched-capacitor converters. ISLPED (2015)
Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. ISLPED (2015)
Visvesh S. Sathe
Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability. ISLPED (2014)
Kannan A. Sankaragomathi, William Anthony Smith, Brian P. Otis, Visvesh S. Sathe
A deterministic-dither-based, all-digital system for on-chippower supply noise measurement. ISLPED (2014)
Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48 (1) (2013)
Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC (2012)
Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon
at 81% efficiency. ISSCC (2010)
Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits 45 (4) (2010)
Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC (2009)
Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC (2009)
Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits 43 (4) (2008)
Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42 (1) (2007)
Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC (2007)
Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio
A 1.1ghz charge-recovery logic. ISSCC (2006)
Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC (2006)
Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers (2005)
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
A GHz-class charge recovery logic. ISLPED (2005)
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI (2005)
Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky
A synchronous interface for SoCs with multiple clock domains. SoCC (2004)
Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
A 225 MHz resonant clocked ASIC chip. ISLPED (2003)