Debashis Mandal

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 13

Top Topics

Sequential Monte Carlo Methods

Metal Oxide Semiconductor

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Kondapalli Surya Prasad, Pudi Hemanth, Debashis Mandal
A Rail-to-Rail Input Class-AB Linear Amplifier with Improved Bandwidth and Slew-Rate for Envelope Tracking Supply Modulators. ISCAS (2024)
Debashis Mandal, Chandan Mazumdar
Towards an Ontology for Enterprise Level Information Security Policy Analysis. ICISSP (2021)
Shrikant Singh, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC-DC Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier. IEEE J. Solid State Circuits 54 (12) (2019)
Debashis Mandal, Chirag Desai, Bertan Bakkaloglu, Sayfe Kiaei
Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications. ISSCC (2019)
Chengxi Liu, Debashis Mandal, Zhao Yao, Ming Sun, Jim Todsen, Brian Johnson, Sayfe Kiaei, Bertan Bakkaloglu
A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency. IEEE Trans. Circuits Syst. II Express Briefs (6) (2019)
Shrikant Singh, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
Sense resistor-free analog power sensor for boost converter with 14.1% gain error and 9.4% offset error. LASCAS (2018)
Maryam Shafiee, Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Bertan Bakkaloglu, Sule Ozev
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters. ACM Trans. Design Autom. Electr. Syst. 23 (2) (2018)
Navankur Beohar, Venkata N. K. Malladi, Debashis Mandal, Sule Ozev, Bertan Bakkaloglu
Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Ming Sun, Zhe Yang, Kishan Joshi, Debashis Mandal, Philippe Adell, Bertan Bakkaloglu
A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error. IEEE J. Solid State Circuits 52 (11) (2017)
Michael Cheah, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
Ripple Digitally Controlled LDO With Active Ripple Suppression. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
ChaiYong Lim, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. ISLPED (2015)
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
Spur reduction in frequency synthesizer with an array of switched capacitors. Int. J. Circuit Theory Appl. 43 (12) (2015)
Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu, Sule Ozev
Disturbance-free BIST for loop characterization of DC-DC buck converters. VTS (2015)
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
Prediction of reference spur in frequency synthesisers. IET Circuits Devices Syst. 9 (2) (2015)
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
Spur reducing architecture of frequency synthesiser using switched capacitors. IET Circuits Devices Syst. 8 (4) (2014)
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
Spur suppression in frequency synthesizer using switched capacitor array. ISOCC (2012)
Debashis Mandal, T. K. Bhattacharyya
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design. J. Comput. 3 (4) (2008)
Debashis Mandal, T. K. Bhattacharyya
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer. VLSI Design (2007)
T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor. VLSI Design (2006)
Debashis Mandal, Pradip Mandal
High voltage tolerant output buffer design for mixed voltage interfaces. ISCAS (5) (2005)