Jae-sun Seo

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 104

Top Venues

Publications

Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hassan, Shixing Yu, Han-Sok Suh, Xiaofeng Hu, Jae-sun Seo
Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design. CoRR (2024)
Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro 44 (2) (2024)
Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hassan, Shixing Yu, Han-Sok Suh, Xiaofeng Hu, Jae-sun Seo
Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design. MLSys (2024)
Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. DATE (2023)
Jian Meng, Li Yang, Kyungmin Lee, Jinwoo Shin, Deliang Fan, Jae-sun Seo
Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training. NeurIPS (2023)
Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
Transformer-based Selective Super-Resolution for Efficient Image Refinement. CoRR (2023)
Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao
3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression. A-SSCC (2023)
Tianyi Zhang, Kishore Kasichainula, Dong-Woo Jee, Injune Yeo, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention. ISCAS (2023)
Gopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao
FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix. DATE (2023)
Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR (2023)
Ahmed Hasssan, Jian Meng, Yu Cao, Jae-sun Seo
Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder. IEEECONF (2022)
Fan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption. ASP-DAC (2022)
Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. ICCAD (2022)
Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Han-Sok Suh, Shihui Yin, Gokul Krishnan, Frank Liu, Jae-sun Seo, Yu Cao
Efficient continual learning at the edge with progressive segmented training. Neuromorph. Comput. Eng. 2 (4) (2022)
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. CICC (2022)
Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Kevin Cao, Deliang Fan
XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method. DAC (2022)
Jian Meng, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, Jae-sun Seo
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. IEEE Micro 42 (1) (2022)
Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC (2022)
Li Yang, Jian Meng, Jae-sun Seo, Deliang Fan
Get More at Once: Alternating Sparse Training with Gradient Correction. NeurIPS (2022)
Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR (2021)
Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL (2021)
Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran
Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks. CoRR (2021)
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits (2021)
Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran
Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. ISCAS (2021)
Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. DAC (2021)
Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS (2021)
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR (2021)
Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. IRPS (2021)
Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR (2021)
Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. FPT (2021)
Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. FPL (2021)
Usama Awais, Jae-sun Seo
Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators. MWSCAS (2020)
Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. IEEE J. Solid State Circuits 55 (10) (2020)
Deepak Kadetotad, Jian Meng, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity. INTERSPEECH (2020)
Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Gaurav Srivastava, Chisung Bae, Sang Joon Kim, Jae-sun Seo
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. IEEE Trans. Biomed. Circuits Syst. 14 (2) (2020)
Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops (2020)
Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. IEEE J. Solid State Circuits 55 (7) (2020)
Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. DATE (2020)
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test 37 (6) (2020)
Colby R. Banbury, Vijay Janapa Reddi, Max Lam, William Fu, Amin Fazel, Jeremy Holleman, Xinyuan Huang, Robert Hurtado, David Kanter, Anton Lokhmotov, David A. Patterson, Danilo Pau, Jae-sun Seo, Jeff Sieracki, Urmish Thakker, Marian Verhelst, Poonam Yadav
Benchmarking TinyML Systems: Challenges and Direction. CoRR (2020)
Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction. IRPS (2020)
Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
Online Knowledge Acquisition with the Selective Inherited Model. IJCNN (2020)
Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo
Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI (2020)
Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39 (6) (2019)
Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo
Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. ACSSC (2019)
Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS (2019)
Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED (2019)
Chia-Yu Chen, Boris Murmann, Jae-sun Seo, Hoi-Jun Yoo
Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL (2019)
Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits 54 (8) (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR (2019)
Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina
FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning. MLSys (2019)
Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. ACM Great Lakes Symposium on VLSI (2019)
Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. ISCAS (2019)
Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning. CoRR (2019)
Mingoo Seok, Minhao Yang, Zhewei Jiang, Aurel A. Lazar, Jae-sun Seo
Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks. VLSI-DAT (2019)
Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR (2019)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. 15 (2) (2019)
Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. ICASSP (2019)
Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS (2018)
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC (2018)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Avesta Sasan, Qi Zhu, Yanzhi Wang, Jae-sun Seo, Tinoosh Mohsenin
Low Power and Trusted Machine Learning. ACM Great Lakes Symposium on VLSI (2018)
Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP (2018)
Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. 14 (4) (2018)
Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo
Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression. CoRR (2018)
Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale
Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE (2018)
Mohit Shah, Sairam Arunachalam, Jingcheng Wang, David T. Blaauw, Dennis Sylvester, Hun-Seok Kim, Jae-sun Seo, Chaitali Chakrabarti
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware. J. Signal Process. Syst. 90 (5) (2018)
Arindam Basu, Meng-Fan Chang, Elisabetta Chicca, Tanay Karnik, Hai Helen Li, Jae-sun Seo
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (1) (2018)
Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Helen Li, Jae-sun Seo, Chang Song
Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (1) (2018)
Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR (2018)
Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD (2018)
Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62 (2018)
Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities. IEEE J. Solid State Circuits 52 (10) (2017)
Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo
Low-power neuromorphic speech recognition engine with coarse-grain sparsity. ASP-DAC (2017)
Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS (2017)
Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao
Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing 267 (2017)
Shihui Yin, Chisung Bae, Sang Joon Kim, Jae-sun Seo
Designing ECG-based physical unclonable function for security of wearable devices. EMBC (2017)
Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED (2017)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS (2017)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA (2017)
Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo
Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs. IWANN (2) (2017)
Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. ACSSC (2017)
Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS (2017)
Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR (2017)
Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. DATE (2017)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL (2017)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC (2017)
Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24 (9) (2016)
Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL (2016)
Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo
Bi-Level Rare Temporal Pattern Detection. ICDM (2016)
Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability. A-SSCC (2016)
Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD (2016)
Ricardo Tapiador, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs. CoRR (2016)
Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo
Reducing the Model Order of Deep Neural Networks Using Information Theory. CoRR (2016)
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA (2016)
Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao
Ranking the parameters of deep neural networks using the fisher information. ICASSP (2016)

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Publication Activity (10 Years)

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Jae-sun Seo