Abinash Mohanty

ORCID

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 12

Top Venues

ISCAS

IRPS

IEEE Trans. Circuits Syst. I Regul. Pap.

CoRR

Arizona State University, Tempe, USA (PHD)

Education History

Arizona State University, Tempe, USA

PHD

Publications

Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL (2021)
Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. CoRR (2019)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP (2018)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS (2017)
Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao
RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC (2017)
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA (2016)
Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
High-performance face detection with CPU-FPGA acceleration. ISCAS (2016)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty, Xixiang Feng, Runsheng Wang, Ru Huang, Yu Cao
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. IRPS (2015)
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE (2015)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS (2014)
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA (2014)

Abinash Mohanty.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Abinash Mohanty