Pai-Yu Chen

Publication Activity (10 Years)

Years Active: 2014-2019
Publications (10 Years): 17

Top Topics

Synaptic Plasticity

Parallel Architecture

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pai-Yu Chen, Shimeng Yu
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures. IEEE Des. Test 36 (3) (2019)
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC (2018)
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Pai-Yu Chen, Shimeng Yu
Reliability perspective of resistive synaptic devices on the neuromorphic system performance. IRPS (2018)
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC (2018)
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Rui Liu, Pai-Yu Chen, Shimeng Yu
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. ISCAS (2017)
Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu
Energy-Efficient Adaptive Computing With Multifunctional Memory. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Pai-Yu Chen, Zhiwei Li, Shimeng Yu
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE (2016)
Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD (2016)
Pai-Yu Chen, Ligang Gao, Shimeng Yu
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. IEEE Trans. Multi Scale Comput. Syst. 2 (4) (2016)
Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS (2016)
Pai-Yu Chen, Shimeng Yu
Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. ISCAS (2016)
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. ACM Great Lakes Symposium on VLSI (2016)
Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST (2015)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD (2015)
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE (2015)
Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. ISCAS (2015)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS (2014)
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA (2014)
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD (2014)