Xiaochen Peng

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 41

Top Topics

Inference Engine

Backward Chaining

Top Venues

Publications

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC (2024)
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. ACM Trans. Design Autom. Electr. Syst. 27 (4) (2022)
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. AICAS (2021)
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
Compute-in-Memory: From Device Innovation to 3D System Integration. ESSDERC (2021)
Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. 3DIC (2021)
Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-Sun Seo
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. DATE (2021)
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. Frontiers Artif. Intell. 4 (2021)
Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. ISCAS (2021)
Shimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo
RRAM for Compute-in-Memory: From Inference to Training. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. IRPS (2021)
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. ISCAS (2021)
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. ACM Trans. Design Autom. Electr. Syst. 26 (6) (2021)
Anni Lu, Xiaochen Peng, Shimeng Yu
Compute-in-RRAM with Limited On-chip Resources. AICAS (2021)
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. ICCAD (2020)
Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. CICC (2020)
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. ISCAS (2020)
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training. CoRR (2020)
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. DAC (2020)
Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-Sun Seo, Shimeng Yu
A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. ISCAS (2020)
Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. IEEE Trans. Computers 69 (7) (2020)
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. MEMSYS (2020)
Xiaochen Peng, Rui Liu, Shimeng Yu
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. DATE (2020)
Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti
: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS (2019)
Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. DAC (2019)
Yandong Luo, Xiaochen Peng, Shimeng Yu
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations. ICONS (2019)
Xiaochen Peng, Rui Liu, Shimeng Yu
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. ISCAS (2019)
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. MEMSYS (2019)
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC (2018)
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Xiaochen Peng, Shimeng Yu
Benchmark of RRAM based Architectures for Dot-Product Computation. APCCAS (2018)
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Manqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. SiPS (2018)
Jiyong Woo, Xiaochen Peng, Shimeng Yu
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. ISCAS (2018)
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE (2018)
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC (2018)