Hongwu Jiang

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 29

Top Topics

Electric Arc Furnace

Inference Engine

Top Venues

IEEE J. Solid State Circuits

Publications

Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Shanshi Huang, Hongwu Jiang, Shimeng Yu
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57 (2) (2022)
Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. IEEE J. Solid State Circuits 57 (9) (2022)
Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. IEEE Des. Test 39 (2) (2022)
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. ESSCIRC (2022)
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. ACM Trans. Design Autom. Electr. Syst. 27 (4) (2022)
Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. VLSI Technology and Circuits (2022)
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (4) (2022)
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. AICAS (2021)
Shanshi Huang, Hongwu Jiang, Shimeng Yu
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. NVMSA (2021)
Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. CICC (2021)
Shanshi Huang, Hongwu Jiang, Shimeng Yu
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. CoRR (2021)
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSDERC (2021)
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. Frontiers Artif. Intell. 4 (2021)
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSCIRC (2021)
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. ISCAS (2021)
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. ICCAD (2020)
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC (2020)
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. ISCAS (2020)
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training. CoRR (2020)
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. DAC (2020)
Hongwu Jiang, Rui Liu, Shimeng Yu
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. MWSCAS (2020)
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. IEEE Trans. Computers 69 (7) (2020)
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. MEMSYS (2020)
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. DATE (2020)
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. MEMSYS (2019)