Rui Liu

Publication Activity (10 Years)

Years Active: 2015-2020
Publications (10 Years): 20

Top Topics

Memory Requirements

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55 (1) (2020)
Hongwu Jiang, Rui Liu, Shimeng Yu
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. MWSCAS (2020)
Xiaochen Peng, Rui Liu, Shimeng Yu
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC (2019)
Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti
: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Rui Liu, Can Li, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lu, John Paul Strachan
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization. CoRR (2019)
Xiaochen Peng, Rui Liu, Shimeng Yu
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. ISCAS (2019)
Zhilu Ye, Rui Liu, Hugh J. Barnaby, Shimeng Yu
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference. IRPS (2019)
Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2019)
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC (2018)
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC (2018)
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE (2018)
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC (2018)
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module. AsianHOST (2017)
Rui Liu, Pai-Yu Chen, Shimeng Yu
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. ISCAS (2017)
Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Rui Liu, Heng-Yuan Lee, Shimeng Yu
Analyzing inference robustness of RRAM synaptic array in low-precision neural network. ESSDERC (2017)
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. HOST (2016)
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. ACM Great Lakes Symposium on VLSI (2016)
Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST (2015)
Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. ISCAS (2015)